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* | Check that whiteboxes are synthesisableEddie Hung2019-06-141-4/+8
* | Get rid of compiler warningsEddie Hung2019-06-141-2/+2
* | Cover __APPLE__ too for little to big endianEddie Hung2019-06-141-4/+9
* | Further cleanup based on @daveshah1Eddie Hung2019-06-141-27/+21
* | Resolve comments from @daveshah1Eddie Hung2019-06-141-14/+8
* | Remove WIP ABC9 flop supportEddie Hung2019-06-141-33/+33
* | CleanupEddie Hung2019-06-141-1/+0
* | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-06-141-2/+1
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| * | ecp5: Add abc9 optionDavid Shah2019-06-141-2/+1
* | | Cleanup/optimise toposort in write_xaigerEddie Hung2019-06-141-54/+47
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* | Remove unnecessary undriven_bits.insertEddie Hung2019-06-121-4/+1
* | write_xaiger to preserve POs even if driven by constantEddie Hung2019-06-121-7/+6
* | Add a couple more testsEddie Hung2019-06-121-21/+18
* | More write_xaiger cleanupEddie Hung2019-06-121-40/+12
* | Cleanup write_xaigerEddie Hung2019-06-121-92/+6
* | ConsistencyEddie Hung2019-06-121-1/+1
* | Add log_assert to ensure no loopsEddie Hung2019-06-041-1/+15
* | Only toposort builtin and abc typesEddie Hung2019-06-041-6/+9
* | When creating new holes cell, inherit parameters tooEddie Hung2019-06-031-1/+3
* | ABC9 to understand flopsEddie Hung2019-05-311-46/+27
* | Merge branch 'xaig' into xc7muxEddie Hung2019-05-311-8/+79
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| * | Fix abc9 with (* keep *) wiresEddie Hung2019-04-231-6/+14
| * | Revert "Temporarily remove 'r' extension"Eddie Hung2019-04-221-7/+77
* | | Fix issue where keep signal became PI, but also box was adding CI driverEddie Hung2019-05-301-5/+19
* | | Do not re-sort box_module portsEddie Hung2019-05-301-4/+6
* | | Carry in/out to be the last input/output for chains to be preservedEddie Hung2019-05-301-0/+38
* | | Fix abc_test024Eddie Hung2019-05-291-4/+5
* | | Fix for abc9_test022Eddie Hung2019-05-281-2/+6
* | | Small improvementEddie Hung2019-05-281-4/+2
* | | Update from masterEddie Hung2019-05-281-59/+56
* | | Map file to include boxes not CI/COEddie Hung2019-05-271-45/+38
* | | Instantiate cell type (from sym file) otherwise 'clean' warningsEddie Hung2019-05-271-2/+4
* | | Add 'cinput' and 'coutput' to symbols file for boxesEddie Hung2019-05-271-34/+24
* | | Fix "a" connectivityEddie Hung2019-05-261-5/+30
* | | Fix padding, remove CIs from undriven_bits before erasing undriven POsEddie Hung2019-05-261-14/+8
* | | Fix "a" extensionEddie Hung2019-05-261-8/+18
* | | Fix "write_xaiger", and to write each box contents into holesEddie Hung2019-05-251-39/+62
* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-252-7/+27
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| * | Fix handling of offset and upto module ports in write_blif, fixes #1040Clifford Wolf2019-05-251-6/+20
| * | Add proper error message for btor recursion_guardClifford Wolf2019-05-241-1/+7
* | | Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7muxEddie Hung2019-05-231-3/+7
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| * | Fix static shift operands, neg result type, minor formattingJim Lawson2019-05-211-3/+7
* | | Pad all boxes so that all input/output connections specifiedEddie Hung2019-05-211-22/+67
* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-213-11/+129
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| * | Merge pull request #991 from kristofferkoch/gcc9-warningsClifford Wolf2019-05-081-1/+2
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| | * | Fix all warnings that occurred when compiling with gcc9Kristoffer Ellersgaard Koch2019-05-081-1/+2
| * | | Fix handling of partial init attributes in write_verilog, fixes #997Clifford Wolf2019-05-071-1/+2
| * | | Add "real" keyword to ilang formatClifford Wolf2019-05-061-1/+4
| * | | Improve write_verilog specify supportClifford Wolf2019-05-041-15/+71
| * | | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-031-25/+62
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