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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-04 12:01:25 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-04 12:01:25 -0700 |
| commit | 7b186740d33972612cfc9f2ebe31258edb0cca2b (patch) | |
| tree | 709c073b7003962c606626d64da35efe87a5126a /backends | |
| parent | 1b836c93bbaa3c85d4730b0251aed64cdf207422 (diff) | |
| download | yosys-7b186740d33972612cfc9f2ebe31258edb0cca2b.tar.gz yosys-7b186740d33972612cfc9f2ebe31258edb0cca2b.tar.bz2 yosys-7b186740d33972612cfc9f2ebe31258edb0cca2b.zip | |
Add log_assert to ensure no loops
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 4d45bb650..bf2f9f1bc 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -334,7 +334,21 @@ struct XAigerWriter pool<RTLIL::Module*> abc_carry_modules; - toposort.sort(); +#if 0 + toposort.analyze_loops = true; +#endif + bool no_loops = toposort.sort(); +#if 0 + unsigned i = 0; + for (auto &it : toposort.loops) { + log(" loop %d", i++); + for (auto cell : it) + log(" %s", log_id(cell)); + log("\n"); + } +#endif + log_assert(no_loops); + for (auto cell_name : toposort.sorted) { RTLIL::Cell *cell = module->cell(cell_name); RTLIL::Module* box_module = module->design->module(cell->type); |