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* AigMaker refactoringClifford Wolf2015-06-101-1/+1
* Added "json -aig"Clifford Wolf2015-06-101-9/+63
* $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-081-54/+108
* Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-041-14/+16
* Improvements in BLIF front-endClifford Wolf2015-05-241-0/+1
* Some fixes for $mem in verilog back-endClifford Wolf2015-05-201-19/+23
* Merge pull request #63 from wluker/verilog-backend-memClifford Wolf2015-05-111-1/+2
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| * Fixed bug in $mem cell verilog code generation.luke whittlesey2015-05-111-11/+12
* | Disabled broken $mem support in verilog backendClifford Wolf2015-05-101-11/+11
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* Made changes recommended by Clifford Wolf ...luke whittlesey2015-05-101-22/+11
* Verilog backend for $mem cells should now be able to handle differentluke whittlesey2015-05-081-50/+105
* Added support for $mem cells in the verilog backend.luke whittlesey2015-05-071-1/+120
* Minor fixes in handling of "init" attributeClifford Wolf2015-04-091-7/+7
* Removed "techmap -share_map" (use "-map +/filename" instead)Clifford Wolf2015-04-081-1/+1
* Added "port_directions" to write_json outputClifford Wolf2015-04-061-0/+20
* Added "init" attribute support to verilog backendClifford Wolf2015-04-041-0/+5
* Update READMEAhmed Irfan2015-04-031-1/+1
* Delete btor.ysAhmed Irfan2015-04-031-18/+0
* Update READMEAhmed Irfan2015-04-031-1/+1
* separated memory next from write cellAhmed Irfan2015-04-031-7/+55
* Added Verilog backend $dffsr supportClifford Wolf2015-03-181-1/+51
* Documentation for JSON format, added attributesClifford Wolf2015-03-061-16/+156
* Json bugfixClifford Wolf2015-03-031-1/+1
* Json backend improvementsClifford Wolf2015-03-031-4/+12
* Added write_blif -attrClifford Wolf2015-03-021-18/+33
* Added JSON backendClifford Wolf2015-03-022-0/+262
* Added $assume support to write_smt2Clifford Wolf2015-02-261-4/+19
* Minor "write_smt2" help msg changeClifford Wolf2015-02-221-1/+1
* Added "<mod>_a" and "<mod>_i" to write_smt2 outputClifford Wolf2015-02-221-23/+149
* Fixed "write_verilog -attr2comment" handling of "*/" in stringsClifford Wolf2015-02-131-2/+4
* Added EDIF backend support for multi-bit cell portsClifford Wolf2015-02-011-11/+10
* Shorter "dump" optionsClifford Wolf2015-01-311-4/+4
* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-242-2/+4
* Added dict/pool.sort()Clifford Wolf2015-01-242-50/+26
* Cosmetic changes in verilog output formatClifford Wolf2015-01-021-5/+10
* Fixed memory->start_offset handlingClifford Wolf2015-01-011-0/+2
* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-262-42/+42
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-1/+1
* Various fixes and improvements in "write_smt2 -bv"Clifford Wolf2014-12-253-11/+43
* Various fixes and improvements in write_smt2Clifford Wolf2014-12-252-32/+88
* Added support for most BV cell types to write_smt2Clifford Wolf2014-12-251-14/+221
* Added "write_smt2 -bv" and other write_smt2 improvementsClifford Wolf2014-12-251-172/+153
* Added write_smt2 (only gate level logic supported so far)Clifford Wolf2014-12-242-0/+353
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-1/+1
* Added $dffe support to write_verilogClifford Wolf2014-12-201-3/+14
* Fixed another bug in write_blif handling of $lut cellsClifford Wolf2014-12-191-1/+1
* Fixed writing of $lut cells in BLIF backendClifford Wolf2014-12-171-7/+7
* Added "write_blif -undef" and support for special "-" true/false/undef typeClifford Wolf2014-12-141-13/+33
* Added "write_blif -blackbox"Clifford Wolf2014-12-141-2/+16
* Added "blif -unbuf" featureClifford Wolf2014-12-141-0/+19
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