iCE40/yosys - [no description]

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	Commit message (Expand)	Author	Age	Files	Lines
*	json: Update format documentation.	Marcelina Kościelnicka	2020-04-15	1	-12/+32
*	json: Change compat mode to directly emit ints <= 32 bits	R. Ou	2020-02-09	1	-3/+3
*	json: remove the 32-bit parameter special case	Marcin Kościelnicki	2020-02-01	1	-10/+28
*	Implement improved JSON attr/param encoding	Clifford Wolf	2019-08-01	1	-13/+37
*	Fix json formatting	Miodrag Milanovic	2019-06-21	1	-1/+1
*	Add upto and offset to JSON ports	Miodrag Milanovic	2019-06-21	1	-0/+4
*	Added JSON upto and offset	Clifford Wolf	2019-06-21	1	-0/+4
*	Support filename rewrite in backends	Ben Widawsky	2019-06-18	1	-0/+1
*	Merge pull request #591 from hzeller/virtual-override	Clifford Wolf	2018-08-15	1	-4/+4
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\| *	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-4/+4
* \|	Fix use of signed integers in JSON back-end	Clifford Wolf	2018-08-14	1	-1/+3
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*	Add attributes and parameter support to JSON front-end	Clifford Wolf	2017-07-10	1	-0/+2
*	Improved write_json help message	Clifford Wolf	2016-12-29	1	-0/+4
*	write_json: also write module attributes.	whitequark	2016-07-12	1	-2/+6
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	user-facing spelling fixes	Sebastian Kuzminsky	2016-02-28	1	-3/+3
*	Another block of spelling fixes	Larry Doolittle	2015-08-14	1	-1/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
*	Improvements in cellaigs.cc and "json -aig"	Clifford Wolf	2015-06-11	1	-6/+63
*	AigMaker refactoring	Clifford Wolf	2015-06-10	1	-1/+1
*	Added "json -aig"	Clifford Wolf	2015-06-10	1	-9/+63
*	Added "port_directions" to write_json output	Clifford Wolf	2015-04-06	1	-0/+20
*	Documentation for JSON format, added attributes	Clifford Wolf	2015-03-06	1	-16/+156
*	Json bugfix	Clifford Wolf	2015-03-03	1	-1/+1
*	Json backend improvements	Clifford Wolf	2015-03-03	1	-4/+12
*	Added JSON backend	Clifford Wolf	2015-03-02	1	-0/+259

lass="k">parameter [18431:0] INIT = 18432'bx; parameter TRANSP2 = 0; input CLK2; input CLK3; input [CFG_ABITS-1:0] A1ADDR; input [CFG_DBITS-1:0] A1DATA; input [CFG_ENABLE_A-1:0] A1EN; input [CFG_ABITS-1:0] B1ADDR; output [CFG_DBITS-1:0] B1DATA; input B1EN; localparam CLKAMUX = CLKPOL2 ? "CLKA" : "INV"; localparam CLKBMUX = CLKPOL3 ? "CLKB" : "INV"; localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE"; generate if (CFG_DBITS == 1) begin DP16KD #( `include "bram_init_1_2_4.vh" .DATA_WIDTH_A(1), .DATA_WIDTH_B(1), .CLKAMUX(CLKAMUX), .CLKBMUX(CLKBMUX), .WRITEMODE_A(WRITEMODE_A), .WRITEMODE_B("READBEFOREWRITE"), .GSR("DISABLED") ) _TECHMAP_REPLACE_ ( `include "bram_conn_1.vh" .CLKA(CLK2), .CLKB(CLK3), .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1), .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1), .RSTA(1'b0), .RSTB(1'b0) ); end else if (CFG_DBITS == 2) begin DP16KD #( `include "bram_init_1_2_4.vh" .DATA_WIDTH_A(2), .DATA_WIDTH_B(2), .CLKAMUX(CLKAMUX), .CLKBMUX(CLKBMUX), .WRITEMODE_A(WRITEMODE_A), .WRITEMODE_B("READBEFOREWRITE"), .GSR("DISABLED") ) _TECHMAP_REPLACE_ ( `include "bram_conn_2.vh" .CLKA(CLK2), .CLKB(CLK3), .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1), .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1), .RSTA(1'b0), .RSTB(1'b0) ); end else if (CFG_DBITS <= 4) begin DP16KD #( `include "bram_init_1_2_4.vh" .DATA_WIDTH_A(4), .DATA_WIDTH_B(4), .CLKAMUX(CLKAMUX), .CLKBMUX(CLKBMUX), .WRITEMODE_A(WRITEMODE_A), .WRITEMODE_B("READBEFOREWRITE"), .GSR("DISABLED") ) _TECHMAP_REPLACE_ ( `include "bram_conn_4.vh" .CLKA(CLK2), .CLKB(CLK3), .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1), .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1), .RSTA(1'b0), .RSTB(1'b0) ); end else if (CFG_DBITS <= 9) begin DP16KD #( `include "bram_init_9_18_36.vh" .DATA_WIDTH_A(9), .DATA_WIDTH_B(9), .CLKAMUX(CLKAMUX), .CLKBMUX(CLKBMUX), .WRITEMODE_A(WRITEMODE_A), .WRITEMODE_B("READBEFOREWRITE"), .GSR("DISABLED") ) _TECHMAP_REPLACE_ ( `include "bram_conn_9.vh" .CLKA(CLK2), .CLKB(CLK3), .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1), .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1), .RSTA(1'b0), .RSTB(1'b0) ); end else if (CFG_DBITS <= 18) begin DP16KD #( `include "bram_init_9_18_36.vh" .DATA_WIDTH_A(18), .DATA_WIDTH_B(18), .CLKAMUX(CLKAMUX), .CLKBMUX(CLKBMUX), .WRITEMODE_A(WRITEMODE_A), .WRITEMODE_B("READBEFOREWRITE"), .GSR("DISABLED") ) _TECHMAP_REPLACE_ ( `include "bram_conn_18.vh" .CLKA(CLK2), .CLKB(CLK3), .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1), .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1), .RSTA(1'b0), .RSTB(1'b0) ); end else begin wire TECHMAP_FAIL = 1'b1; end endgenerate endmodule