iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	kernel: use more ID::*	Eddie Hung	2020-04-02	1	-1/+1
*	Clean up pseudo-private member usage in `backends/edif/edif.cc`.	Alberto Gonzalez	2020-04-01	1	-23/+18
*	edif: more resilience to mismatched port connection sizes.	Marcin Kościelnicki	2020-02-06	1	-16/+27
*	Preserve wires with keep attribute in EDIF back-end	Claire Wolf	2020-01-29	1	-9/+34
*	Merge pull request #1629 from YosysHQ/mwk/edif-z	Claire Wolf	2020-01-21	1	-0/+2
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\| *	edif: Just ignore connections to 'z	Marcin Kościelnicki	2020-01-13	1	-0/+2
* \|	remove whitespace	Miodrag Milanovic	2020-01-10	1	-1/+1
* \|	Export wire properties as well in EDIF	Miodrag Milanovic	2020-01-10	1	-26/+38
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*	Add "whitebox" attribute, add "read_verilog -wb"	Clifford Wolf	2019-04-18	1	-3/+3
*	Fix "write_edif -gndvccy"	Clifford Wolf	2019-03-01	1	-1/+1
*	Add "write_edif -gndvccy"	Clifford Wolf	2019-01-17	1	-5/+13
*	Add "write_edif -attrprop"	Clifford Wolf	2018-10-05	1	-11/+28
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Fix the fixed handling of x-bits in EDIF back-end	Clifford Wolf	2017-07-11	1	-1/+0
*	Fix handling of x-bits in EDIF back-end	Clifford Wolf	2017-07-11	1	-1/+11
*	Add generation of logic cells to EDIF back-end runtest.py	Clifford Wolf	2017-03-19	1	-2/+6
*	Fix EDIF: portRef member 0 is always the MSB bit	Clifford Wolf	2017-03-19	2	-13/+14
*	Add simple EDIF test case generator and checker	Clifford Wolf	2017-03-18	1	-0/+113
*	Improve "write_edif" help message	Clifford Wolf	2017-02-25	1	-7/+2
*	Move EdifNames out of double-private namespace	Clifford Wolf	2017-02-25	1	-48/+45
*	Clean up edif code, swap bit indexing of "upto" ports	Clifford Wolf	2017-02-25	1	-17/+35
*	Did as you requested, /but/...	Johann Klammer	2017-02-24	1	-45/+29
*	add options for edif flavors	Johann Klammer	2017-02-23	1	-4/+60
*	Add warning about x/z bits left unconnected in EDIF output	Clifford Wolf	2017-02-14	1	-2/+5
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Fixed some typos	Clifford Wolf	2016-04-05	1	-1/+1
*	Added "write_edif -nogndvcc"	Clifford Wolf	2016-03-08	1	-17/+34
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
*	Added EDIF backend support for multi-bit cell ports	Clifford Wolf	2015-02-01	1	-11/+10
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-1/+1
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23	1	-69/+69
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-2/+2
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-1/+1
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+0
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-6/+6
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-3/+3
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-2/+2
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-2/+2
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-9/+6
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-1/+0
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-6/+3
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-1/+1
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-1/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-10/+10
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-10/+10
*	Better handling of nameDef and nameRef in edif backend	Clifford Wolf	2014-02-21	1	-21/+27
*	Fixed instantiating multi-bit ports in edif backend	Clifford Wolf	2014-02-21	1	-2/+4
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-2/+2