| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | cxxrtl: keep the memory write queue sorted on insertion. | Asu | 2020-04-22 | 1 | -3/+5 |
| * | cxxrtl: use one delta cycle for immediately converging netlists. | whitequark | 2020-04-21 | 1 | -3/+4 |
| * | cxxrtl: provide attributes to black box factories, too. | whitequark | 2020-04-19 | 1 | -10/+10 |
| * | cxxrtl: add simple black box support. | whitequark | 2020-04-18 | 1 | -0/+53 |
| * | cxxrtl: make ROMs writable, document memory::operator[]. | whitequark | 2020-04-16 | 1 | -2/+5 |
| * | write_cxxrtl: improve writable memory handling. | whitequark | 2020-04-09 | 1 | -39/+64 |
| * | write_cxxrtl: avoid undefined behavior on out-of-bounds memory access. | whitequark | 2020-04-09 | 1 | -8/+13 |
| * | write_cxxrtl: statically schedule comb logic and localize wires. | whitequark | 2020-04-09 | 1 | -0/+4 |
| * | write_cxxrtl: new backend. | whitequark | 2020-04-09 | 1 | -0/+1104 |
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