iCE40/yosys - [no description]

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* \| \| \| \| \|	Bump version	github-actions[bot]	2022-10-31	1	-1/+1
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* \| \| \| \| \|	Add missing log_dump_val_worker forward declarations	Claire Xenia Wolf	2022-10-30	1	-0/+5
\| \| \| \| \| \| \| \| \| \| \| \| \| #include <linux/module.h> #include "libgcc.h" long long __ashrdi3(long long u, word_type b) { DWunion uu, w; word_type bm; if (b == 0) return u; uu.ll = u; bm = 32 - b; if (bm <= 0) { /* w.s.high = 1..1 or 0..0 */ w.s.high = uu.s.high >> 31; w.s.low = uu.s.high >> -bm; } else { const unsigned int carries = (unsigned int) uu.s.high << bm; w.s.high =
* \| \| \| \| \|	Bump version	github-actions[bot]	2022-10-15	1	-1/+1
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* \| \| \| \| \|	Merge pull request #3511 from YosysHQ/improve_edif	Miodrag Milanović	2022-10-14	1	-1/+31
\|\ \ \ \ \ \ \| \|/ / / / / \|/\| \| \| \| \|	verific: enable import all cells
\| * \| \| \| \|	Skip verific primitives and operators import by default	Miodrag Milanovic	2022-10-14	1	-0/+1
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\| * \| \| \| \|	Add option to import all cells from all libraries	Miodrag Milanovic	2022-10-14	1	-1/+30
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* \| \| \| \|	Bump version	github-actions[bot]	2022-10-13	1	-1/+1
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* \| \| \| \|	Merge pull request #3510 from jix/ff_witness_fixes	Jannis Harder	2022-10-12	4	-12/+29
\|\ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \|	smt2/smtbmc: Fix FF witness data for fine grained or multi chunk FFs
\| * \| \| \| \|	smt2/smtbmc: Fix FF witness data for fine grained or multi chunk FFs	Jannis Harder	2022-10-12	4	-12/+29
\|/ / / / / \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	The witness metadata was missing fine grained FFs completely and for coarse grained FFs where the output connection has multiple chunks it lacked the offset of the chunk within the SMT expression. This fixes both, the later by adding an "smtoffset" field to the metadata.
* / / / /	github: issues: added an OS dropdown to the issue template	Aki Van Ness	2022-10-12	1	-1/+13
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* \| \| \|	Merge pull request #3502 from jix/equiv_opt_fixes	Jannis Harder	2022-10-11	28	-267/+207
\|\ \ \ \ \| \| \| \| \| \| \| \| \| \|	equiv_opt and clk2fflogic fixes
\| * \| \| \|	Reenable existing equiv_opt tests	Jannis Harder	2022-10-07	13	-54/+52
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\| * \| \| \|	Fix tests for check in equiv_opt	Jannis Harder	2022-10-07	13	-15/+31
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\| * \| \| \|	Add "check -assert" to equiv_opt	Claire Xenia Wolf	2022-10-07	1	-1/+13
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
\| * \| \| \|	Re-enable opt_dff_sr equiv_opt checks	Claire Xenia Wolf	2022-10-07	1	-13/+12
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
\| * \| \| \|	Exclude primary inputs from quiv_make rewiring	Claire Xenia Wolf	2022-10-07	1	-0/+7
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
\| * \| \| \|	Revert "Merge pull request #641 from tklam/master"	Claire Xenia Wolf	2022-10-07	1	-81/+5
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This reverts commit 08be796cb8b1890923e459cda92211fda763f0c1, reversing changes made to 38dbb44fa0815b1fe80e68e17798aaa341d998cd. This fixes #2728. PR #641 did not actually "fix" #639. The actual issue in #639 is not equiv_make, but assumptions in equiv_simple that are not true for the test case provided in #639.
\| * \| \| \|	clk2fflogic: Always correctly handle simultaneously changing signals	Jannis Harder	2022-10-07	1	-103/+87
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This is a complete rewrite of the FF replacing code. The previous implementation tried to implement the negative hold time by wrapping async control signals individually with pulse stretching. This did not correctly model the interaction between different simultaneously changing inputs (e.g. a falling ALOAD together with a changing AD would load the changed AD instead of the value AD had when ALOAD was high; a falling CLR could mask a raising SET for one cycle; etc.). The new approach first has the logic for all updates using only sampled values followed by the logic for all updates using only current values. That way, e.g., a falling ALOAD will load the sampled AD value but a still active ALOAD will load the current AD value. The new code also has deterministic behavior for the initial state: no operation is active when that operation would depend on a specific previous signal value. This also means clk2fflogic will no longer generate any additional uninitialized FFs. I also documented the negative hold time behavior in the help message, copying the relevant part from async2sync's help messages.
* \| \| \| \|	Bump version	github-actions[bot]	2022-10-11	1	-1/+1
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* \| \| \| \|	Merge pull request #3508 from YosysHQ/aki/rm_protobuf	Miodrag Milanović	2022-10-10	5	-562/+0
\|\ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \|	backends: protobuf: removed protobuf backend
\| * \| \| \| \|	backends: protobuf: removed protobuf backend	Aki Van Ness	2022-10-10	5	-562/+0
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* \| \| \| \|	fix whitespace	Miodrag Milanovic	2022-10-10	1	-1/+1
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* \| \| \| \|	Merge pull request #3452 from ALGCDG/master	Miodrag Milanović	2022-10-10	2	-1/+17
\|\ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \|	Add BLIF names command input plane size check