| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | | * | | | | | | | | | | | | | | | | | | Make pmgen support files more generic | Eddie Hung | 2019-04-25 | 2 | -6/+9 | |
| | * | | | | | | | | | | | | | | | | | | | synth_xilinx to call bitblast_shiftx | Eddie Hung | 2019-04-25 | 1 | -1/+4 | |
| | * | | | | | | | | | | | | | | | | | | | Remove topo sort no-loop assertion, with test | Eddie Hung | 2019-04-24 | 4 | -14/+76 | |
| | * | | | | | | | | | | | | | | | | | | | Add -nocarry option to synth_xilinx | Eddie Hung | 2019-04-24 | 1 | -5/+14 | |
| | * | | | | | | | | | | | | | | | | | | | Fix abc9 with (* keep *) wires | Eddie Hung | 2019-04-23 | 2 | -6/+52 | |
| | * | | | | | | | | | | | | | | | | | | | Refactor into AigerReader::post_process() | Eddie Hung | 2019-04-23 | 2 | -249/+161 | |
| | * | | | | | | | | | | | | | | | | | | | Tweak | Eddie Hung | 2019-04-22 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | | | Fix for A_WIDTH == 2 but B_WIDTH==3 | Eddie Hung | 2019-04-22 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | | | Trim A_WIDTH by Y_WIDTH-1 | Eddie Hung | 2019-04-22 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | | | Add comment | Eddie Hung | 2019-04-22 | 1 | -0/+3 | |
| | * | | | | | | | | | | | | | | | | | | | Fix for mux_case_* mappings | Eddie Hung | 2019-04-22 | 1 | -17/+9 | |
| | * | | | | | | | | | | | | | | | | | | | Fix for non-pow2 width muxes | Eddie Hung | 2019-04-22 | 1 | -9/+18 | |
| | * | | | | | | | | | | | | | | | | | | | Add synth_xilinx -nomux option | Eddie Hung | 2019-04-22 | 2 | -4/+18 | |
| | * | | | | | | | | | | | | | | | | | | | Cleanup, call pmux2shiftx even without -nosrl | Eddie Hung | 2019-04-22 | 6 | -45/+30 | |
| | * | | | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-22 | 31 | -283/+953 | |
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| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/xc7srl' into xc7mux | Eddie Hung | 2019-04-22 | 77 | -348/+4702 | |
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| | * | | | | | | | | | | | | | | | | | | | | | Add MUXCY and XORCY to cells_box.v | Eddie Hung | 2019-04-16 | 2 | -0/+15 | |
| | * | | | | | | | | | | | | | | | | | | | | | Fix wire numbering | Eddie Hung | 2019-04-16 | 1 | -1/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | Do not put constants into output_bits | Eddie Hung | 2019-04-16 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | Remove write_verilog call | Eddie Hung | 2019-04-16 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | Fix spacing | Eddie Hung | 2019-04-16 | 2 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-16 | 2 | -3/+1 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | NULL check before use | Eddie Hung | 2019-04-16 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | WIP for box support | Eddie Hung | 2019-04-16 | 1 | -36/+93 | |
| | * | | | | | | | | | | | | | | | | | | | | | | ABC to read_box before reading netlist | Eddie Hung | 2019-04-16 | 1 | -1/+3 | |
| | * | | | | | | | | | | | | | | | | | | | | | | Make cells.box whiteboxes not blackboxes | Eddie Hung | 2019-04-16 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | | read_verilog cells_box.v before techmap | Eddie Hung | 2019-04-16 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | synth_xilinx: before abc read +/xilinx/cells_box.v | Eddie Hung | 2019-04-16 | 1 | -0/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | Add +/xilinx/cells_box.v containing models for ABC boxes | Eddie Hung | 2019-04-16 | 2 | -0/+11 | |
| | * | | | | | | | | | | | | | | | | | | | | | | For 'stat' do not count modules with abc_box_id | Eddie Hung | 2019-04-16 | 1 | -0/+3 | |
| | * | | | | | | | | | | | | | | | | | | | | | | Do not call abc on modules with abc_box_id attr | Eddie Hung | 2019-04-16 | 1 | -0/+3 | |
| | * | | | | | | | | | | | | | | | | | | | | | | Revert "Add abc_box_id attribute to MUXF7/F8 cells" | Eddie Hung | 2019-04-16 | 1 | -2/+0 | |
| | * | | | | | | | | | | | | | | | | | | | | | | Use abc_box_id | Eddie Hung | 2019-04-15 | 1 | -2/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | Check abc_box_id attr | Eddie Hung | 2019-04-15 | 1 | -1/+16 | |
| | * | | | | | | | | | | | | | | | | | | | | | | Add abc_box_id attribute to MUXF7/F8 cells | Eddie Hung | 2019-04-15 | 1 | -0/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-15 | 9 | -100/+246 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | PI before CI | Eddie Hung | 2019-04-12 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-04-12 | 1 | -3/+9 | |
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| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux | Eddie Hung | 2019-04-11 | 1 | -1/+0 | |
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| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux | Eddie Hung | 2019-04-11 | 6 | -8/+93 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Fix cells_map.v some more | Eddie Hung | 2019-04-11 | 1 | -7/+7 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | More fine tuning | Eddie Hung | 2019-04-11 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Fix cells_map.v | Eddie Hung | 2019-04-11 | 1 | -7/+7 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Fix typo | Eddie Hung | 2019-04-11 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Juggle opt calls in synth_xilinx | Eddie Hung | 2019-04-11 | 2 | -30/+35 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-10 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | WIP for cells_map.v -- maybe working? | Eddie Hung | 2019-04-10 | 1 | -32/+27 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1 | Eddie Hung | 2019-04-10 | 1 | -31/+38 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix for when B_SIGNED = 1 | Eddie Hung | 2019-04-10 | 1 | -1/+8 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Update doc for synth_xilinx | Eddie Hung | 2019-04-10 | 1 | -7/+8 | |
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index : iCE40/yosys | |
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