| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | xilinx_dsp: Initial DSP48A/DSP48A1 support. | Marcin Kościelnicki | 2019-12-22 | 10 | -14/+921 | |
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| * / | xilinx: Test our DSP48A/DSP48A1 simulation models. | Marcin Kościelnicki | 2019-12-23 | 5 | -7/+362 | |
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| * | Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanup | Eddie Hung | 2019-12-20 | 1 | -19/+27 | |
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| | * | write_xaiger: only instantiate each whitebox cell type once | Eddie Hung | 2019-12-20 | 1 | -19/+27 | |
| * | | Add abc9_arrival times for RAM{32,64}M | Eddie Hung | 2019-12-20 | 1 | -24/+10 | |
| * | | Add RAM{32,64}M to abc9_map.v | Eddie Hung | 2019-12-20 | 1 | -0/+78 | |
| * | | Put specify/endspecify inside `` | Eddie Hung | 2019-12-20 | 1 | -4/+4 | |
| * | | Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut | Eddie Hung | 2019-12-20 | 1 | -19/+18 | |
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| | * | Interpret "abc9 -lut" as lut string only if [0-9:] | Eddie Hung | 2019-12-18 | 1 | -19/+18 | |
| * | | Merge pull request #1587 from YosysHQ/revert-1558-eddie/xaiger_cleanup | Eddie Hung | 2019-12-20 | 4 | -39/+21 | |
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| | * | | Revert "Optimise write_xaiger" | Eddie Hung | 2019-12-20 | 4 | -39/+21 | |
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| * | | Fix linking with Python 3.8 | Graham Edgecombe | 2019-12-20 | 1 | -0/+7 | |
| * | | Add PYTHON_CONFIG variable to the Makefile | Graham Edgecombe | 2019-12-20 | 1 | -17/+18 | |
| * | | Merge pull request #1581 from YosysHQ/clifford/fix1565 | Eddie Hung | 2019-12-19 | 1 | -1/+1 | |
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| | * | | Fix sim for assignments with lhs<rhs size, fixes #1565 | Clifford Wolf | 2019-12-17 | 1 | -1/+1 | |
| * | | | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup | Eddie Hung | 2019-12-19 | 4 | -21/+39 | |
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| | * | | | Stray newline | Eddie Hung | 2019-12-06 | 1 | -1/+0 | |
| | * | | | write_xaiger to inst each cell type once, do not call techmap/aigmap | Eddie Hung | 2019-12-06 | 1 | -21/+25 | |
| | * | | | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger | Eddie Hung | 2019-12-06 | 3 | -0/+15 | |
| * | | | | Merge pull request #1569 from YosysHQ/eddie/fix_1531 | Eddie Hung | 2019-12-19 | 2 | -0/+50 | |
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| | * | | | | Stray log_dump | Eddie Hung | 2019-12-11 | 1 | -1/+0 | |
| | * | | | | Preserve size of $genval$-s in for loops | Eddie Hung | 2019-12-11 | 1 | -0/+17 | |
| | * | | | | Add testcase | Eddie Hung | 2019-12-11 | 1 | -0/+34 | |
| * | | | | | Merge pull request #1571 from YosysHQ/eddie/fix_1570 | Eddie Hung | 2019-12-19 | 1 | -3/+1 | |
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| | * | | | | | Make SV2017 compliant courtesy of @wsnyder | Eddie Hung | 2019-12-12 | 1 | -3/+1 | |
| * | | | | | | xilinx: Add simulation models for remaining CLB primitives. | Marcin Kościelnicki | 2019-12-19 | 3 | -156/+210 | |
| * | | | | | | xilinx_dffopt: Keep order of LUT inputs. | Marcin Kościelnicki | 2019-12-19 | 1 | -16/+30 | |
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| * | | | | | Add "scratchpad" to CHANGELOG | Eddie Hung | 2019-12-18 | 1 | -0/+1 | |
| * | | | | | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2019-12-18 | 24 | -84/+1071 | |
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| | * \ \ \ \ | Merge pull request #1563 from YosysHQ/dave/async-prld | David Shah | 2019-12-18 | 2 | -4/+28 | |
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| | | * | | | | | ecp5: Add support for mapping PRLD FFs | David Shah | 2019-12-07 | 2 | -4/+28 | |
| | * | | | | | | Merge pull request #1572 from nakengelhardt/scratchpad_pass | Eddie Hung | 2019-12-18 | 3 | -0/+136 | |
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| | | * | | | | | | use extra_args | N. Engelhardt | 2019-12-18 | 1 | -1/+1 | |
| | | * | | | | | | add assert option to scratchpad command | N. Engelhardt | 2019-12-16 | 3 | -19/+49 | |
| | | * | | | | | | add periods and newlines to help message | N. Engelhardt | 2019-12-13 | 1 | -5/+5 | |
| | | * | | | | | | add test and make help message more verbose | N. Engelhardt | 2019-12-12 | 2 | -1/+20 | |
| | | * | | | | | | add a command to read/modify scratchpad contents | N. Engelhardt | 2019-12-12 | 2 | -0/+87 | |
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| | * | | | | | | Merge pull request #1584 from YosysHQ/mwk/xilinx-flaky-test | Eddie Hung | 2019-12-18 | 1 | -2/+4 | |
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| | | * | | | | | | tests/xilinx: fix flaky mux test | Marcin Kościelnicki | 2019-12-18 | 1 | -2/+4 | |
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| | * | | | | | | xilinx: Add xilinx_dffopt pass (#1557) | Marcin Kościelnicki | 2019-12-18 | 11 | -27/+638 | |
| | * | | | | | | xilinx: Improve flip-flop handling. | Marcin Kościelnicki | 2019-12-18 | 8 | -49/+242 | |
| | * | | | | | | Send people to symbioticeda.com instead of verific.com | Clifford Wolf | 2019-12-18 | 2 | -5/+26 | |
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| * / | | | | | Cleanup | Eddie Hung | 2019-12-17 | 1 | -11/+7 | |
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| * | | | | | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram | Eddie Hung | 2019-12-16 | 13 | -65/+529 | |
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| | * \ \ \ \ | Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xil... | Eddie Hung | 2019-12-16 | 1 | -2/+8 | |
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| | | * | | | | | Populate DID/DOD even if unused | Eddie Hung | 2019-12-16 | 1 | -2/+8 | |
| | * | | | | | | Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q | Eddie Hung | 2019-12-16 | 2 | -6/+6 | |
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| | * | | | | | Disable RAM16X1D test | Eddie Hung | 2019-12-13 | 1 | -17/+17 | |
| | * | | | | | Disable RAM16X1D match rule; carry-over from LUT4 arches | Eddie Hung | 2019-12-13 | 1 | -6/+9 | |
| | * | | | | | RAM64M8 to also have [5:0] for address | Eddie Hung | 2019-12-13 | 1 | -8/+8 | |
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index : iCE40/yosys | |
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