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| author | Clifford Wolf <clifford@clifford.at> | 2019-12-17 17:32:48 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-12-17 17:36:30 +0100 |
| commit | 41ed6ca7a5a18aa3a2ce42e76012c43fdf2de73b (patch) | |
| tree | 51a0232c112ee38594d99c1ce42e971f09e06689 | |
| parent | a73f96594f4688afc85098b485ef7788e79f5c33 (diff) | |
| download | yosys-41ed6ca7a5a18aa3a2ce42e76012c43fdf2de73b.tar.gz yosys-41ed6ca7a5a18aa3a2ce42e76012c43fdf2de73b.tar.bz2 yosys-41ed6ca7a5a18aa3a2ce42e76012c43fdf2de73b.zip | |
Fix sim for assignments with lhs<rhs size, fixes #1565
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | passes/sat/sim.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 4c3022c70..d5634b26d 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -230,7 +230,7 @@ struct SimInstance bool did_something = false; sig = sigmap(sig); - log_assert(GetSize(sig) == GetSize(value)); + log_assert(GetSize(sig) <= GetSize(value)); for (int i = 0; i < GetSize(sig); i++) if (state_nets.at(sig[i]) != value[i]) { |