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| * | | Fix read_aiger -- create zero driver, fix init width, parse 'b'Eddie Hung2019-06-072-13/+52
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| * | | Use ABC to convert from AIGER to VerilogEddie Hung2019-06-071-2/+3
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| * | | Use ABC to convert AIGER to Verilog, then sat against YosysEddie Hung2019-06-071-21/+15
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| * | | Add symbols to AIGER test inputs for ABCEddie Hung2019-06-0722-8/+40
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* | | Merge pull request #1077 from YosysHQ/clifford/pr983Clifford Wolf2019-06-079-3/+93
|\ \ \ | | | | | | | | elaboration system tasks
| * | | Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-074-50/+38
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-0710-5/+107
| |\ \ \ | | | | | | | | | | | | | | | clifford/pr983
| | * | | Initial implementation of elaboration system tasksUdi Finkelstein2019-05-0310-5/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
* | | | | Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
|/ / / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge branch 'tux3-implicit_named_connection'Clifford Wolf2019-06-074-3/+40
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| * | | | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-073-13/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵Clifford Wolf2019-06-075-4/+52
| |\ \ \ \ | | |_|/ / | |/| | | | | | | | into tux3-implicit_named_connection
| | * | | SystemVerilog support for implicit named port connectionstux32019-06-065-12/+59
| | | | | | | | | | | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.
* | | | | Merge pull request #1076 from thasti/centos7-build-fixClifford Wolf2019-06-071-1/+0
|\ \ \ \ \ | |/ / / / |/| | | | Fix pyosys-build on CentOS7
| * | | | remove boost/log/exceptions.hpp from wrapper generatorStefan Biereigel2019-06-071-1/+0
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* | | | Merge pull request #1060 from antmicro/parsing_attr_on_port_connClifford Wolf2019-06-0614-10/+279
|\ \ \ \ | | | | | | | | | | Added support for parsing attributes on port connections.
| * | | | Fixed memory leak.Maciej Kurc2019-06-051-0/+4
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ↵Maciej Kurc2019-06-044-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | just for parsing Verilog. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | | | Added tests for attributesMaciej Kurc2019-06-039-0/+219
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | | | Added support for parsing attributes on port connections.Maciej Kurc2019-05-311-10/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | | | | Merge pull request #1073 from whitequark/ecp5-diamond-iobDavid Shah2019-06-061-0/+15
|\ \ \ \ \ | | | | | | | | | | | | ECP5: implement most Diamond I/O buffer primitives
| * | | | | ECP5: implement all Diamond I/O buffer primitives.whitequark2019-06-061-0/+15
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* | | | | | Merge pull request #1071 from YosysHQ/eddie/fix_1070Clifford Wolf2019-06-061-2/+2
|\ \ \ \ \ \ | | | | | | | | | | | | | | Fix typo in opt_rmdff causing register to be incorrectly removed
| * | | | | | Fix typo in opt_rmdffEddie Hung2019-06-051-2/+2
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* | | | | | | Merge pull request #1072 from YosysHQ/eddie/fix_1069Clifford Wolf2019-06-061-0/+5
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Error out if no top module given before 'sim'
| * | | | | | | Error out if no top module given before 'sim'Eddie Hung2019-06-051-0/+5
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* / / / / / / Missing doc for -tech xilinx in shregmapEddie Hung2019-06-051-0/+3
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* | | | | | Merge pull request #1067 from YosysHQ/clifford/fix1065Eddie Hung2019-06-051-1/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | Suppress driver-driver conflict warning for unknown cell types
| * | | | | | Suppress driver-driver conflict warning for unknown cell types, fixes #1065Clifford Wolf2019-06-051-1/+1
| | |_|/ / / | |/| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Merge pull request #1066 from YosysHQ/clifford/fix1056Clifford Wolf2019-06-051-1/+0
|\ \ \ \ \ \ | | | | | | | | | | | | | | Remove yosys_banner() from python wrapper init
| * | | | | | Remove yosys_banner() from python wrapper init, fixes #1056Clifford Wolf2019-06-051-1/+0
| |/ / / / / | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Major rewrite of wire selection in setundef -initClifford Wolf2019-06-051-30/+89
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Indent fixClifford Wolf2019-06-051-23/+25
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Merge pull request #999 from jakobwenzel/setundefInitFixClifford Wolf2019-06-051-16/+23
|\ \ \ \ \ \ | | | | | | | | | | | | | | initialize more registers in setundef -init
| * | | | | | initialize more registers in setundef -initJakob Wenzel2019-05-091-16/+23
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* | | | | | | Fix typo in fmcombine log message, fixes #1063Clifford Wolf2019-06-051-2/+2
| |/ / / / / |/| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Merge pull request #1062 from tux3/patch-1Clifford Wolf2019-06-041-1/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | README.md: Missing formatting for <tag>
| * | | | | | README.md: Missing formatting for <tag>Tux32019-06-041-1/+1
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* | | | | | Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_mapEddie Hung2019-06-031-6/+5
|\ \ \ \ \ \ | | | | | | | | | | | | | | Execute techmap and arith_map simultaneously
| * | | | | | Remove extra newlineEddie Hung2019-06-031-1/+0
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| * | | | | | Execute techmap and arith_map simultaneouslyEddie Hung2019-06-031-6/+6
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* | | / / / Only support Symbiotic EDA flavored VerificClifford Wolf2019-06-021-0/+8
| |_|/ / / |/| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Fix "tee" handling of log_streamsClifford Wolf2019-05-311-0/+5
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ↵Clifford Wolf2019-05-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fixes #1055 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Merge pull request #1057 from mmicko/fix_478Clifford Wolf2019-05-301-0/+4
|\ \ \ \ \ | | | | | | | | | | | | Aded one more load of .conf to support change of prefix
| * | | | | Aded one more load of .conf to support change of prefixMiodrag Milanovic2019-05-291-0/+4
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* | | | | Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-282-4/+15
|\ \ \ \ \ | | | | | | | | | | | | Do not use shiftmul peepopt pattern when mul result is truncated
| * | | | | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-282-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Merge pull request #1050 from YosysHQ/clifford/wandworClifford Wolf2019-05-289-40/+207
|\ \ \ \ \ \ | | | | | | | | | | | | | | Refactored wand/wor support
| * | | | | | Refactor hierarchy wand/wor handlingClifford Wolf2019-05-283-103/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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