| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | | | | | Update CHANGELOG | David Shah | 2019-07-09 | 1 | -0/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | | | Merge pull request #1163 from whitequark/more-case-attrs | Clifford Wolf | 2019-07-09 | 3 | -16/+28 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | More support for case rule attributes | |||||
| | | * | | | | | | | Merge pull request #1162 from whitequark/rtlil-case-attrs | Clifford Wolf | 2019-07-09 | 3 | -5/+15 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow attributes on individual switch cases in RTLIL | |||||
| | | * | | | | | | | Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire | Clifford Wolf | 2019-07-09 | 1 | -0/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Throw runtime exception when trying to convert inexistend C++ object to Python | |||||
| | | * | | | | | | | Merge pull request #1147 from YosysHQ/clifford/fix1144 | Clifford Wolf | 2019-07-09 | 3 | -82/+26 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve specify dummy parser | |||||
| | | * | | | | | | | Merge pull request #1154 from whitequark/manual-sync-always | Clifford Wolf | 2019-07-09 | 1 | -2/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | manual: explain the purpose of `sync always` | |||||
| | | * | | | | | | | Merge pull request #1153 from YosysHQ/dave/fix_multi_mux | David Shah | 2019-07-09 | 3 | -3/+25 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | memory_dff: Fix checking of feedback mux input when more than one mux | |||||
| | | * | | | | | | | Fix read_verilog assert/assume/etc on default case label, fixes ↵ | Clifford Wolf | 2019-07-09 | 1 | -0/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | YosysHQ/SymbiYosys#53 Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | | | | autotest.sh to define _AUTOTB when test_autotb | Eddie Hung | 2019-07-09 | 1 | -1/+1 | |
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| | | * | | | | | | | Merge pull request #1146 from gsomlo/gls-test-abc-ext | Clifford Wolf | 2019-07-09 | 4 | -8/+29 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | tests: use optional ABCEXTERNAL when specified | |||||
| | | * | | | | | | | Checkout yosys-0.9-rc branch of yosys-tests | Eddie Hung | 2019-07-02 | 1 | -1/+1 | |
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| | | * | | | | | | | Add missing CHANGELOG entries | Eddie Hung | 2019-06-28 | 1 | -0/+3 | |
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| | * | | | | | | | | Merge pull request #1112 from acw1251/pyosys_sigsig_issue | Clifford Wolf | 2019-08-25 | 1 | -16/+10 | |
| | |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | Fixed pyosys commands returning RTLIL::SigSig | |||||
| | | * | | | | | | | | Fixed pyosys commands returning RTLIL::SigSig | acw1251 | 2019-06-19 | 1 | -16/+10 | |
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| | * | | | | | | | | | Merge pull request #1327 from YosysHQ/clifford/pmgen | Clifford Wolf | 2019-08-24 | 5 | -32/+280 | |
| | |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | Add pmgen slices and choices | |||||
| | | * | | | | | | | | | indo -> into | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| | | * | | | | | | | | | Fix port hanlding in pmgen | Clifford Wolf | 2019-08-23 | 1 | -4/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | | | | | | Add pmgen slices and choices | Clifford Wolf | 2019-08-23 | 5 | -28/+277 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | | | | | Add undocumented feature | Eddie Hung | 2019-08-23 | 1 | -0/+8 | |
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| | * | | | | | | | | | Forgot one | Eddie Hung | 2019-08-23 | 1 | -1/+2 | |
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| | * | | | | | | | | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 3 | -14/+28 | |
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| | * | | | | | | | Merge pull request #1326 from mmicko/doc-update | Eddie Hung | 2019-08-23 | 1 | -2/+5 | |
| | |\ \ \ \ \ \ \ | | |/ / / / / / | |/| | | | | | | Make macOS dependency clear | |||||
| | | * | | | | | | Make macOS depenency clear | Miodrag Milanovic | 2019-08-23 | 1 | -2/+5 | |
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| | * | | | | / | Do not propagate mem2reg attribute through to result | Eddie Hung | 2019-08-22 | 2 | -1/+3 | |
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| | * | | | | | Spelling | Eddie Hung | 2019-08-22 | 1 | -2/+2 | |
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| | * | | | | | Merge pull request #1322 from mmicko/pyosys_osx | Eddie Hung | 2019-08-22 | 1 | -0/+2 | |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | do not require boost if pyosys is not used | |||||
| | | * | | | | | do not require boost if pyosys is not used | Miodrag Milanovic | 2019-08-22 | 1 | -0/+2 | |
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| | * | | | | | Merge pull request #1319 from TeaEngineering/shuckc/brew-tcl-tk | Eddie Hung | 2019-08-22 | 1 | -0/+1 | |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | require tcl-tk in Brewfile | |||||
| | | * | | | | | require tcl-tk in Brewfile | Chris Shucksmith | 2019-08-22 | 1 | -0/+1 | |
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| | * | | | | | | Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx | Eddie Hung | 2019-08-22 | 2 | -4/+96 | |
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | opt_expr to trim A port of $shiftx/$shift | |||||
| | | * | | | | | | Copy-paste typo | Eddie Hung | 2019-08-22 | 1 | -1/+1 | |
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| | | * | | | | | | Respect opt_expr -keepdc as per @cliffordwolf | Eddie Hung | 2019-08-22 | 2 | -1/+15 | |
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| | | * | | | | | | Handle $shift and Y_WIDTH > 1 as per @cliffordwolf | Eddie Hung | 2019-08-22 | 2 | -5/+51 | |
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| | | * | | | | | | Add cover() | Eddie Hung | 2019-08-22 | 1 | -0/+1 | |
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| | | * | | | | | | Canonical form | Eddie Hung | 2019-08-22 | 1 | -5/+5 | |
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| | | * | | | | | | Add test | Eddie Hung | 2019-08-21 | 1 | -0/+14 | |
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| | | * | | | | | | opt_expr to trim A port of $shiftx if Y_WIDTH == 1 | Eddie Hung | 2019-08-21 | 1 | -0/+17 | |
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| | * | | | | | | | Bump year in copyright notice | Clifford Wolf | 2019-08-22 | 3 | -3/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | | Merge pull request #1289 from mmicko/anlogic_fixes | Clifford Wolf | 2019-08-22 | 5 | -91/+162 | |
| | |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | Anlogic fixes and optimization | |||||
| | | * \ \ \ \ \ \ | Merge remote-tracking branch 'upstream/master' into anlogic_fixes | Miodrag Milanovic | 2019-08-18 | 109 | -3621/+4745 | |
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| | | * | | | | | | | | Proper arith for Anlogic and use standard pass | Miodrag Milanovic | 2019-08-12 | 5 | -91/+162 | |
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| | * | | | | | | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | | | Merge pull request #1281 from mmicko/efinix | Clifford Wolf | 2019-08-22 | 9 | -0/+798 | |
| | |\ \ \ \ \ \ \ \ | | |_|_|_|/ / / / | |/| | | | | | | | Initial support for Efinix Trion series FPGAs | |||||
| | | * | | | | | | | Fix formating | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 | |
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| | | * | | | | | | | one bit enable signal | Miodrag Milanovic | 2019-08-11 | 1 | -1/+1 | |
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| | | * | | | | | | | fix mixing signals on FF mapping | Miodrag Milanovic | 2019-08-11 | 1 | -4/+4 | |
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| | | * | | | | | | | Replaced custom step with setundef | Miodrag Milanovic | 2019-08-11 | 3 | -91/+1 | |
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| | | * | | | | | | | Fixed data width | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 | |
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| | | * | | | | | | | Adding new pass to fix carry chain | Miodrag Milanovic | 2019-08-11 | 3 | -0/+124 | |
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index : iCE40/yosys | |
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