| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #1490 from YosysHQ/clifford/autoname | Clifford Wolf | 2019-11-14 | 3 | -0/+136 |
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| | * | Add "autoname" pass and use it in "synth_ice40" | Clifford Wolf | 2019-11-13 | 3 | -0/+136 |
| * | | Merge pull request #1444 from btut/feature/python_wrappers/globals_and_streams | Clifford Wolf | 2019-11-14 | 1 | -6/+286 |
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| | * \ | Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python... | Benedikt Tutzer | 2019-10-15 | 25 | -61/+345 |
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| | * | | | Fix renaming all classes to Cpp* | Benedikt Tutzer | 2019-10-09 | 1 | -2/+2 |
| | * | | | Expose global variables and allow logging to python streams | Benedikt Tutzer | 2019-10-09 | 1 | -6/+286 |
| * | | | | Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim | Clifford Wolf | 2019-11-14 | 1 | -14/+436 |
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| | * | | | | ice40: Add post-pnr ICESTORM_RAM model and fix FFs | David Shah | 2019-10-23 | 1 | -2/+340 |
| | * | | | | ice40: Support for post-pnr timing simulation | David Shah | 2019-10-23 | 1 | -12/+96 |
| * | | | | | Merge branch 'makaimann-label-bads-btor' | Clifford Wolf | 2019-11-14 | 1 | -1/+6 |
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| | * | | | | | Use cell name for btor bad state props when it is a public name | Clifford Wolf | 2019-11-14 | 1 | -9/+5 |
| | * | | | | | Merge branch 'label-bads-btor' of https://github.com/makaimann/yosys into mak... | Clifford Wolf | 2019-11-14 | 1 | -1/+10 |
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| | * | | | | | Add an info string symbol for bad states in btor backend | Makai Mann | 2019-11-11 | 1 | -1/+10 |
| * | | | | | | Merge pull request #1488 from whitequark/flowmap-fixes | whitequark | 2019-11-13 | 1 | -2/+3 |
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| | * | | | | | flowmap: when doing mincut, ensure source is always in X, not X̅. | whitequark | 2019-11-12 | 1 | -1/+2 |
| | * | | | | | flowmap: don't break if that creates a k+2 (and larger) LUT either. | whitequark | 2019-11-11 | 1 | -1/+1 |
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| * | | | | | Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix | Clifford Wolf | 2019-11-13 | 1 | -6/+10 |
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| | * | | | | | Update fsm_detect bugfix | Clifford Wolf | 2019-11-12 | 1 | -3/+4 |
| | * | | | | | Bugfix in fsm_detect | Clifford Wolf | 2019-11-12 | 1 | -6/+9 |
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| * | | | | | Merge pull request #1484 from YosysHQ/clifford/cmp2luteqne | Clifford Wolf | 2019-11-12 | 6 | -18/+35 |
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| | * | | | | Fixed tests | Miodrag Milanovic | 2019-11-11 | 5 | -17/+34 |
| | * | | | | Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp | Clifford Wolf | 2019-11-11 | 1 | -1/+1 |
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| * | | | | Merge pull request #1470 from YosysHQ/clifford/subpassdoc | Clifford Wolf | 2019-11-10 | 1 | -0/+46 |
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| | * | | | | Add CodingReadme section on script passes | Clifford Wolf | 2019-10-31 | 1 | -0/+46 |
| * | | | | | Add check for valid macro names in macro definitions | Clifford Wolf | 2019-11-07 | 1 | -7/+11 |
| * | | | | | synth_xilinx: Merge blackbox primitive libraries. | Marcin Kościelnicki | 2019-11-06 | 11 | -23234/+29820 |
| * | | | | | Fix write_aiger bug added in 524af21 | Clifford Wolf | 2019-11-04 | 1 | -0/+3 |
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| * | | | | Merge pull request #1393 from whitequark/write_verilog-avoid-init | Clifford Wolf | 2019-10-27 | 1 | -4/+5 |
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| | * | | | | write_verilog: do not print (*init*) attributes on regs. | whitequark | 2019-09-22 | 1 | -4/+5 |
| * | | | | | Improve naming scheme for (VHDL) modules imported from Verific | Clifford Wolf | 2019-10-24 | 1 | -3/+26 |
| * | | | | | Merge pull request #1455 from YosysHQ/dave/ultrascaleplus | David Shah | 2019-10-24 | 9 | -417/+1153 |
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| | * | | | | | xilinx: Add URAM288 mapping for xcup | David Shah | 2019-10-23 | 5 | -2/+92 |
| | * | | | | | xilinx: Add support for UltraScale[+] BRAM mapping | David Shah | 2019-10-23 | 7 | -416/+1062 |
| * | | | | | | Add "verific -L" | Clifford Wolf | 2019-10-24 | 1 | -1/+12 |
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| * | | | | | Bugfix in smtio vcd handling of $-identifiers | Clifford Wolf | 2019-10-23 | 1 | -6/+9 |
| * | | | | | xilinx: Support multiplier mapping for all families. | Marcin Kościelnicki | 2019-10-22 | 9 | -9/+269 |
| * | | | | | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg | Clifford Wolf | 2019-10-22 | 2 | -0/+2 |
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| | * | | | | | Call memory_dff before DSP mapping to reserve registers (fixes #1447) | N. Engelhardt | 2019-10-17 | 2 | -0/+2 |
| * | | | | | | Add "verilog_defines -list" and "verilog_defines -reset" | Clifford Wolf | 2019-10-21 | 1 | -0/+16 |
| * | | | | | | Fix handling of "restrict" in Verific front-end | Clifford Wolf | 2019-10-21 | 1 | -1/+1 |
| * | | | | | | ecp5: Pass -nomfs to abc9 | David Shah | 2019-10-20 | 1 | -2/+2 |
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| * | | | | | Merge pull request #1457 from xobs/python-binary-name | Miodrag Milanović | 2019-10-19 | 6 | -9/+9 |
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| | * | | | | | Makefile: don't assume python is called `python3` | Sean Cross | 2019-10-19 | 6 | -9/+9 |
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| * | | | | | Merge pull request #1454 from YosysHQ/mmicko/common_tests | Miodrag Milanović | 2019-10-18 | 166 | -1763/+455 |
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| | * | | | | | fixed error | Miodrag Milanovic | 2019-10-18 | 1 | -1/+1 |
| | * | | | | | Unify verilog style | Miodrag Milanovic | 2019-10-18 | 11 | -191/+157 |
| | * | | | | | Common memory test now shared | Miodrag Milanovic | 2019-10-18 | 10 | -89/+5 |
| | * | | | | | Remove not needed tests | Miodrag Milanovic | 2019-10-18 | 4 | -52/+0 |
| | * | | | | | Share common tests | Miodrag Milanovic | 2019-10-18 | 103 | -1316/+178 |
| | * | | | | | fix yosys path | Miodrag Milanovic | 2019-10-18 | 1 | -2/+2 |
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index : iCE40/yosys | |
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