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| author | Clifford Wolf <clifford@clifford.at> | 2019-10-21 12:39:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-10-21 12:39:28 +0200 |
| commit | 4033ff8c2ed2d312b0dc54940502c6ff9c34ebe7 (patch) | |
| tree | 5ae077bff5b2f772005a9e7e37157cea4a1ef1f3 | |
| parent | fa989e59e5a37d804d8a82050e022b8f4b7070d8 (diff) | |
| download | yosys-4033ff8c2ed2d312b0dc54940502c6ff9c34ebe7.tar.gz yosys-4033ff8c2ed2d312b0dc54940502c6ff9c34ebe7.tar.bz2 yosys-4033ff8c2ed2d312b0dc54940502c6ff9c34ebe7.zip | |
Fix handling of "restrict" in Verific front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | frontends/verific/verific.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index c5eef4b55..9f9eeb764 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1256,7 +1256,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (inst->Type() == PRIM_SVA_ASSERT || inst->Type() == PRIM_SVA_IMMEDIATE_ASSERT) sva_asserts.insert(inst); - if (inst->Type() == PRIM_SVA_ASSUME || inst->Type() == PRIM_SVA_IMMEDIATE_ASSUME) + if (inst->Type() == PRIM_SVA_ASSUME || inst->Type() == PRIM_SVA_IMMEDIATE_ASSUME || inst->Type() == PRIM_SVA_RESTRICT) sva_assumes.insert(inst); if (inst->Type() == PRIM_SVA_COVER || inst->Type() == PRIM_SVA_IMMEDIATE_COVER) |