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| * verilog: error out when non-ANSI task/func argumentsEddie Hung2020-05-111-1/+5
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| * tests: add #2042 testcaseEddie Hung2020-05-111-0/+12
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| * Setup tests/verilog properlyEddie Hung2020-05-113-0/+24
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* | Merge pull request #2052 from YosysHQ/claire/verific_memfixClaire Wolf2020-05-141-2/+12
|\ \ | | | | | | Add support for non-power-of-two mem chunks in verific importer
| * | Add support for non-power-of-two mem chunks in verific importerClaire Wolf2020-05-141-2/+12
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixesClaire Wolf2020-05-142-12/+32
|\ \ \ | | | | | | | | opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically
| * | | opt_clean: improve warning messageEddie Hung2020-05-142-2/+2
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| * | | opt_clean: add init testEddie Hung2020-05-141-0/+13
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| * | | opt_clean: rminit without -purge; also remove if consistent with const..Eddie Hung2020-05-141-9/+17
| | | | | | | | | | | | | | | | warn otherwise
| * | | opt_clean: really make 'clean' identical to 'opt_clean' by rminit tooEddie Hung2020-05-141-3/+2
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* | | Merge pull request #2027 from YosysHQ/eddie/verilog_neg_uptoClaire Wolf2020-05-144-8/+35
|\ \ \ | |/ / |/| | ast: swap range regardless of range_left >= 0
| * | techlibs/common: more robustness when *_WIDTH = 0Eddie Hung2020-05-053-8/+30
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| * | ast: swap range regardless of range_left >= 0Eddie Hung2020-05-041-1/+1
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| * | test: add failing testEddie Hung2020-05-041-0/+5
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* | | ice40: fix ICESTORM_LC process sensitivityEddie Hung2020-05-121-1/+1
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* | | ice40: fix whitespaceEddie Hung2020-05-121-15/+14
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* | | ecp5: Add missing SERDES parametersDavid Shah2020-05-121-0/+4
| |/ |/| | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #2038 from nakengelhardt/no-libdir-flagClaire Wolf2020-05-081-2/+1
|\ \ | | | | | | Remove yosys libdir from LDFLAGS (and fix a typo)
| * | Remove yosys libdir from LDFLAGS (and fix a typo)N. Engelhardt2020-05-071-2/+1
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* | | Fix clang compiler warningClaire Wolf2020-05-081-2/+2
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | Merge pull request #2022 from Xiretza/fallthroughswhitequark2020-05-085-9/+26
|\ \ \ | | | | | | | | Avoid switch fall-through warnings
| * | | Reorder cases to avoid fall-through warningXiretza2020-05-071-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | log_assert(false) never returns and thus can't fall through, but gcc doesn't seem to think that far. Making it the last case avoids the problem entirely.
| * | | Add YS_FALLTHROUGH macro to mark case fall-throughXiretza2020-05-075-6/+23
| | | | | | | | | | | | | | | | | | | | C++17 introduced [[fallthrough]], GCC and clang had their own vendored attributes before that. MSVC doesn't seem to have such a warning at all.
* | | | intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-079-52/+163
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
* | | Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-079-19/+142
|\ \ \ | | | | | | | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
| * | | Fix the other "opt_expr -fine" bug introduced in 213a89558Claire Wolf2020-05-021-7/+19
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | Add plusargs for output files in test_autotb outputClaire Wolf2020-05-021-3/+10
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | Bugfix in partsel.v signed indices test casesClaire Wolf2020-05-021-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | Fix handling of signed indices in bit slicesClaire Wolf2020-05-021-3/+8
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | Add tests based on the test case from #1990Claire Wolf2020-05-021-0/+46
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-025-7/+22
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed ↵Claire Wolf2020-05-026-7/+57
| | | | | | | | | | | | | | | | | | | | | | | | offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | | Merge pull request #2034 from YosysHQ/eddie/abc_remoteEddie Hung2020-05-071-1/+1
|\ \ \ \ | |_|/ / |/| | | Makefile: git fetch $(ABCURL) explicitly for local ABC checkout
| * | | Makefile: git fetch all commits from $(ABCURL) repoEddie Hung2020-05-061-1/+1
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* | | | Merge pull request #2028 from zachjs/masterEddie Hung2020-05-063-1/+23
|\ \ \ \ | |/ / / |/| | | verilog: allow null gen-if then block
| * | | verilog: allow null gen-if then blockZachary Snow2020-05-063-1/+23
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* | | Merge pull request #2025 from YosysHQ/eddie/frontend_cleanupEddie Hung2020-05-057-31/+34
|\ \ \ | | | | | | | | frontend: cleanup to use more ID::*, more dict<> instead of map<>
| * | | frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-047-31/+34
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* | | Merge pull request #2012 from whitequark/fix-wasi-abc-buildwhitequark2020-05-051-3/+3
|\ \ \ | | | | | | | | Fix WASI builds with abc enabled
| * | | Update ABC to include WASI support fixes.whitequark2020-05-021-1/+1
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| * | | Fix WASI builds with abc enabled.whitequark2020-05-011-2/+2
| | | | | | | | | | | | | | | | This PR works around #2011.
* | | | Merge pull request #2026 from YosysHQ/eddie/scratchpad_abc9_WEddie Hung2020-05-053-11/+34
|\ \ \ \ | | | | | | | | | | synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
| * | | | synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-043-11/+34
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* | | | Merge pull request #2024 from YosysHQ/eddie/primitive_srcEddie Hung2020-05-053-2/+22
|\ \ \ \ | | | | | | | | | | verilog: set src attribute for primitives
| * | | | verilog: set src attribute for primitivesEddie Hung2020-05-042-2/+6
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| * | | | tests: add tests for primitives' srcEddie Hung2020-05-041-0/+16
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* | | | Merge pull request #2023 from YosysHQ/eddie/specify_srcEddie Hung2020-05-052-18/+26
|\ \ \ \ | |/ / / |/| | | verilog: fix specify src attribute
| * | | verilog: fix specify src attributeEddie Hung2020-05-042-18/+26
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* | | Merge pull request #1996 from boqwxp/rtlil_source_locationsEddie Hung2020-05-041-13/+13
|\ \ \ | | | | | | | | frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
| * | | frontend: Include complete source location instead of just ↵Alberto Gonzalez2020-05-011-13/+13
| | | | | | | | | | | | | | | | `location.first_line` in `frontends/ast/genrtlil.cc`.
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