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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-04 10:22:05 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-04 10:22:05 -0700 |
| commit | eca9fc01a78c5cc4c1d8120e2ccdf18211bcef37 (patch) | |
| tree | 2f7baee8ade49e326f002d3fd799f95891ff95e0 | |
| parent | ad8e7878f6321b9c35ae41b651a7da9a733ce4be (diff) | |
| download | yosys-eca9fc01a78c5cc4c1d8120e2ccdf18211bcef37.tar.gz yosys-eca9fc01a78c5cc4c1d8120e2ccdf18211bcef37.tar.bz2 yosys-eca9fc01a78c5cc4c1d8120e2ccdf18211bcef37.zip | |
verilog: set src attribute for primitives
| -rw-r--r-- | frontends/ast/simplify.cc | 4 | ||||
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 837c14ad7..488681649 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1739,8 +1739,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, AstNode *node = children_list[1]; if (op_type != AST_POS) - for (size_t i = 2; i < children_list.size(); i++) + for (size_t i = 2; i < children_list.size(); i++) { node = new AstNode(op_type, node, children_list[i]); + node->location = location; + } if (invert_results) node = new AstNode(AST_BIT_NOT, node); diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4a5aba79e..f2ff685e9 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1747,7 +1747,9 @@ single_prim: /* no name */ { astbuf2 = astbuf1->clone(); ast_stack.back()->children.push_back(astbuf2); - } '(' cell_port_list ')'; + } '(' cell_port_list ')' { + SET_AST_NODE_LOC(astbuf2, @1, @$); + } cell_parameter_list_opt: '#' '(' cell_parameter_list ')' | /* empty */; |