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* Merge pull request #1811 from PeterCrozier/typedef_scopeN. Engelhardt2020-03-306-43/+88
|\ | | | | Support module/package/interface/block scope for typedef names.
| * Inline productions to follow house style.Peter Crozier2020-03-271-33/+29
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| * Error duplicate declarations of a typedef name in the same scope.Peter Crozier2020-03-242-3/+11
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| * Support module/package/interface/block scope for typedef names.Peter Crozier2020-03-236-22/+63
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* | Merge pull request #1778 from rswarbrick/sv-definesN. Engelhardt2020-03-3011-151/+636
|\ \ | | | | | | Add support for SystemVerilog-style `define to Verilog frontend
| * | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-2711-151/+636
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* | | Explicit include of csignalMiodrag Milanovic2020-03-281-0/+1
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* | | windows - there are no stopping signalsMiodrag Milanovic2020-03-281-0/+1
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* | | Merge pull request #1607 from whitequark/simplify-simplify-meminitClaire Wolf2020-03-271-63/+82
|\ \ \ | |/ / |/| | ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
| * | ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.whitequark2020-02-071-65/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
* | | Merge pull request #1815 from boqwxp/fix-ef-optimizeClaire Wolf2020-03-271-1/+7
|\ \ \ | | | | | | | | Fix solver output parsing for exists-forall optimization
| * | | Do not change solver output parsing for non-exists-forall problems.Alberto Gonzalez2020-03-261-2/+6
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| * | | Skip reading stdout from the solver that if it isn't a line reading only ↵Alberto Gonzalez2020-03-261-1/+3
| | | | | | | | | | | | | | | | "sat", "unsat", or "unknown".
* | | | Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fixClaire Wolf2020-03-262-1/+19
|\ \ \ \ | |/ / / |/| | | techmap: Fix cell names with _TECHMAP_REPLACE_.*
| * | | techmap: Fix cell names with _TECHMAP_REPLACE_.*Marcin Kościelnicki2020-03-232-1/+19
| | | | | | | | | | | | | | | | Fixes #1804.
* | | | Revert part of 0fda8308 from #1746 that broke other smtbmc flowsClaire Wolf2020-03-241-3/+1
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | | Merge pull request #1763 from boqwxp/issue1762N. Engelhardt2020-03-238-12/+73
|\ \ \ \ | |_|_|/ |/| | | Closes #1762. Adds warnings for `select` arguments not matching any object and for `add` command when no modules selected
| * | | Do not warn on empty selection with prefixed `arg_memb`.Alberto Gonzalez2020-03-232-1/+7
| | | | | | | | | | | | | | | | Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
| * | | Suppress warnings for empty `select` arguments when `-count` or `-assert-*` ↵Alberto Gonzalez2020-03-232-4/+7
| | | | | | | | | | | | | | | | options are set.
| * | | Add tests for `select` command warnings.Alberto Gonzalez2020-03-234-0/+13
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| * | | Warn on empty selection for `add` command.Alberto Gonzalez2020-03-232-6/+40
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| * | | Add N:* to select language, fix some old codeClaire Wolf2020-03-171-4/+9
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | | Merge pull request #1803 from Grazfather/typedefN. Engelhardt2020-03-2312-40/+124
|\ \ \ \ | | | | | | | | | | Support standard typedef grammar (Fixed)
| * | | | Simplify was not being called for packages. Broke typedef enums.Peter Crozier2020-03-221-5/+8
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| * | | | Build pkg_user_types before parsing in case of changes in the design.Peter Crozier2020-03-221-6/+3
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| * | | | Clear pkg_user_types if no packages following a 'design -reset-vlog'.Peter2020-03-222-0/+5
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| * | | | Revert typedef tests to standard grammar.Peter2020-03-227-25/+26
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| * | | | Parser changes to support typedef.Peter2020-03-224-10/+88
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* | | | | Merge pull request #1805 from hofstee/masterN. Engelhardt2020-03-232-2/+2
|\ \ \ \ \ | | | | | | | | | | | | fix typo in `write_smt2` help
| * | | | | fix typo in `write_smt2` helpTeguh Hofstee2020-03-232-2/+2
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* | | | | | Merge pull request #1785 from boqwxp/mitercc_cleanupN. Engelhardt2020-03-231-60/+56
|\ \ \ \ \ \ | |/ / / / / |/| | | | | Clean up pseudo-private member usage in `passes/sat/miter.cc`.
| * | | | | Clean up pseudo-private member usage in `passes/sat/miter.cc`.Alberto Gonzalez2020-03-191-60/+56
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* | | | | | iopadmap: Attempt to give new wires/cells meaningful namesR. Ou2020-03-221-6/+18
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* | | | | Merge pull request #1794 from YosysHQ/dave/mince-abc9-fixDavid Shah2020-03-212-0/+18
|\ \ \ \ \ | | | | | | | | | | | | ice40: Map unmapped 'mince' DFFs to gate level
| * | | | | Add test for abc9+mince issueDavid Shah2020-03-201-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | ice40: Map unmapped 'mince' DFFs to gate levelDavid Shah2020-03-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | Merge pull request #1795 from smunaut/fix_abc9_spramEddie Hung2020-03-201-2/+2
|\ \ \ \ \ \ | |/ / / / / |/| | | | | ice40: Fix typos in SPRAM ABC9 timing specs
| * | | | | ice40: Fix typos in SPRAM ABC9 timing specsSylvain Munaut2020-03-201-2/+2
|/ / / / / | | | | | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | / / / xilinx: Mark IOBUFDS.IOB as external padMarcin Kościelnicki2020-03-202-1/+2
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* | | | Merge pull request #1788 from YosysHQ/eddie/fix_ndebugEddie Hung2020-03-192-2/+2
|\ \ \ \ | | | | | | | | | | Fix NDEBUG warnings
| * | | | Fix NDEBUG warningsEddie Hung2020-03-192-2/+2
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* | | | | fsm_extract: Initialize celltypes with full design.Marcin Kościelnicki2020-03-192-5/+34
| | | | | | | | | | | | | | | | | | | | Fixes #1781.
* | | | | Merge pull request #1787 from YosysHQ/mmicko/lexer_depsMiodrag Milanović2020-03-191-1/+1
|\ \ \ \ \ | |/ / / / |/| | | | Add dependency to verilog_lexer.cc
| * | | | Add one mode dependencyMiodrag Milanovic2020-03-191-1/+1
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* | | | Merge pull request #1774 from boqwxp/execN. Engelhardt2020-03-193-0/+210
|\ \ \ \ | | | | | | | | | | Add `exec` command to allow running shell commands from inside Yosys scripts
| * | | | Update copyright and license header.Alberto Gonzalez2020-03-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | I hereby assign to Claire Wolf the copyright for all work I did on `passes/cmds/exec.cc`. In the event that this copyright assignment is not legally valid, I offer this work under the ISC license.
| * | | | Clean up `exec` code according to review.Alberto Gonzalez2020-03-181-5/+18
| | | | | | | | | | | | | | | | | | | | Co-Authored-By: Miodrag Milanović <mmicko@gmail.com>
| * | | | Add test for `exec` command.Alberto Gonzalez2020-03-161-0/+6
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| * | | | Allow specifying multiple regexes to match in `exec` command output, and ↵Alberto Gonzalez2020-03-161-33/+67
| | | | | | | | | | | | | | | | | | | | also to specify regexes that must _not_ match.
| * | | | Add `exec` command to run shell commands.Alberto Gonzalez2020-03-162-0/+157
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