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| author | David Shah <dave@ds0.me> | 2020-03-20 20:35:28 +0000 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2020-03-20 20:35:28 +0000 |
| commit | fa77fb857b42b32f3d518da8a590c406ddc8eee9 (patch) | |
| tree | faa54abf668f67251c3a2cab36e3c8e143f6cff3 | |
| parent | e813624f21f2c6daa7af0befb50553bb668367fd (diff) | |
| download | yosys-fa77fb857b42b32f3d518da8a590c406ddc8eee9.tar.gz yosys-fa77fb857b42b32f3d518da8a590c406ddc8eee9.tar.bz2 yosys-fa77fb857b42b32f3d518da8a590c406ddc8eee9.zip | |
Add test for abc9+mince issue
Signed-off-by: David Shah <dave@ds0.me>
| -rw-r--r-- | tests/various/ice40_mince_abc9.ys | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/tests/various/ice40_mince_abc9.ys b/tests/various/ice40_mince_abc9.ys new file mode 100644 index 000000000..408e16f05 --- /dev/null +++ b/tests/various/ice40_mince_abc9.ys @@ -0,0 +1,17 @@ +read_verilog <<EOT + +module top(input clk, ce, input [2:0] a, b, output reg [2:0] q); + + reg [2:0] aa, bb; + + always @(posedge clk) begin + if (ce) begin + aa <= a; + end + bb <= b; + q <= aa + bb; + end +endmodule +EOT + +synth_ice40 -abc9 -dffe_min_ce_use 4 |