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* ecp5 to use -max_iter 1Eddie Hung2019-08-203-4/+3
* ecp5 to use abc_map.v and _unmap.vEddie Hung2019-08-207-14/+89
* Add (* abc_arrival=<int> *) docEddie Hung2019-08-201-0/+5
* Add reference to FD* timingEddie Hung2019-08-201-0/+2
* Remove sequential extensionEddie Hung2019-08-209-730/+68
* Remove SRL* delays from cells_sim.vEddie Hung2019-08-201-5/+3
* retime_mode -> dff_modeEddie Hung2019-08-201-7/+7
* LUTMUX -> LUTMUX6Eddie Hung2019-08-201-2/+2
* Cleanup techmap in map_lutsEddie Hung2019-08-201-3/+5
* Move `techmap abc_map.v` into map_lutsEddie Hung2019-08-201-1/+2
* Remove delays from abc_map.vEddie Hung2019-08-201-5/+2
* TypoEddie Hung2019-08-201-1/+1
* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-205-16/+23
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| * Merge pull request #1209 from YosysHQ/eddie/synth_xilinxEddie Hung2019-08-205-16/+23
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| | * Merge remote-tracking branch 'origin/master' into eddie/synth_xilinxEddie Hung2019-08-20191-4502/+7003
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| | * | Bump abc to fix &mfs bugEddie Hung2019-07-251-1/+1
| | * | Update changelogEddie Hung2019-07-221-3/+4
| | * | Update Makefile tooEddie Hung2019-07-181-2/+2
| | * | Add CHANGELOG entryEddie Hung2019-07-181-0/+3
| | * | Work in progress for renaming labels/options in synth_xilinxEddie Hung2019-07-183-14/+17
* | | | Do not sigmap!Eddie Hung2019-08-201-2/+2
* | | | Deprecate `abc_scc_break` attributeEddie Hung2019-08-201-8/+0
* | | | Wrap SRL{16,32} tooEddie Hung2019-08-203-7/+98
* | | | Wrap LUTRAMs in order to capture comb/seq behaviourEddie Hung2019-08-205-36/+200
* | | | Minor refactorEddie Hung2019-08-201-7/+6
* | | | Add LUTRAM delaysEddie Hung2019-08-201-3/+6
* | | | Fix use of {CLK,EN}_POLARITY, also add a FIXMEEddie Hung2019-08-201-65/+13
* | | | Remove mapping rulesEddie Hung2019-08-201-33/+0
* | | | Remove -icellsEddie Hung2019-08-201-2/+2
* | | | Use abc_{map,unmap,model}.vEddie Hung2019-08-208-141/+334
* | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-2024-112/+857
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| * | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactorEddie Hung2019-08-206-104/+138
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| | * | | Clarify with 'only'Eddie Hung2019-08-191-1/+1
| | * | | Update docEddie Hung2019-08-191-3/+4
| | * | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithroEddie Hung2019-08-194-12/+12
| * | | | Merge pull request #1298 from YosysHQ/clifford/pmgenClifford Wolf2019-08-2012-93/+790
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| | * \ \ \ Merge branch 'master' into clifford/pmgenClifford Wolf2019-08-2013-39/+85
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| * | | | | Add test case for real parametersClifford Wolf2019-08-201-1/+10
| * | | | | Merge pull request #1308 from jakobwenzel/real_paramsClifford Wolf2019-08-201-1/+4
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| | * | | | | handle real values when deriving ast modulesJakob Wenzel2019-08-191-1/+4
| * | | | | | Merge pull request #1309 from whitequark/proc_clean-fix-1268whitequark2019-08-206-2/+37
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| | * | | | | proc_clean: fix order of switch insertion.whitequark2019-08-196-2/+37
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| | | * | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgenClifford Wolf2019-08-19110-2078/+3173
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| | | * | | | Add test for pmtest_test "reduce" demo patternClifford Wolf2019-08-171-0/+21
| | | * | | | Refactor pmgen rollback mechanismClifford Wolf2019-08-171-32/+21
| | | * | | | Improvements in "test_pmgen -generate"Clifford Wolf2019-08-171-3/+23
| | | * | | | Add pmgen "fallthrough" statementClifford Wolf2019-08-172-3/+17
| | | * | | | Add help() callEddie Hung2019-08-161-0/+1
| | | * | | | Minor bugfix in "test_pmgen -generate"Clifford Wolf2019-08-161-1/+1
| | | * | | | Add pmgen finish statement, return number of matchesClifford Wolf2019-08-164-82/+116