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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 18:22:58 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 18:22:58 -0700 |
| commit | 343039496baf434beca8c2fb3c275a60365f9496 (patch) | |
| tree | e9e6e615775283668a9c8091921661da02e49053 | |
| parent | 091bf4a18b2f4bf84fe62b61577c88d961468b3c (diff) | |
| download | yosys-343039496baf434beca8c2fb3c275a60365f9496.tar.gz yosys-343039496baf434beca8c2fb3c275a60365f9496.tar.bz2 yosys-343039496baf434beca8c2fb3c275a60365f9496.zip | |
Add reference to FD* timing
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index d879a56ee..6aba5a4b2 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -211,6 +211,8 @@ endmodule `endif +// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250 + module FDRE ((* abc_arrival=303 *) output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; |