iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| *	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06	5	-6/+80
\| *	Various improvements in memory_dff pass	Clifford Wolf	2014-08-06	1	-21/+22
\| *	Various fixes and improvements in wreduce pass	Clifford Wolf	2014-08-05	1	-29/+47
\| *	Removed old "constmap" from wreduce code	Clifford Wolf	2014-08-05	1	-3/+2
\| *	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05	4	-12/+93
\| *	Cleanups and improvements in wreduce pass	Clifford Wolf	2014-08-05	1	-47/+77
\| *	Added mux support to wreduce command	Clifford Wolf	2014-08-05	1	-36/+82
\| *	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05	4	-9/+90
\| *	Fixed AST handling of variables declared inside a functions main block	Clifford Wolf	2014-08-05	2	-3/+16
\| *	Added "show -signed"	Clifford Wolf	2014-08-04	1	-5/+17
\| *	Added support for non-standard "module mod_name(...);" syntax	Clifford Wolf	2014-08-04	2	-1/+12
\| *	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04	2	-9/+21
\| *	Fixed "share" for memory read ports	Clifford Wolf	2014-08-03	1	-0/+7
\| *	Added "wreduce" to some of the standard test benches	Clifford Wolf	2014-08-03	3	-2/+3
\| *	Progress in "wreduce" pass	Clifford Wolf	2014-08-03	1	-43/+16
\| *	Added "wreduce" command (work in progress)	Clifford Wolf	2014-08-03	2	-0/+253
\| *	Added query() API to ModIndex	Clifford Wolf	2014-08-03	1	-8/+46
\| *	Added ID() macro for static IdStrings	Clifford Wolf	2014-08-03	1	-0/+3
\| *	Implemented recursive techmap	Clifford Wolf	2014-08-03	2	-17/+63
\| *	Fixes in show command (related to new IdString)	Clifford Wolf	2014-08-03	1	-20/+18
\| *	Implemented simplemap support for "techmap -extern"	Clifford Wolf	2014-08-02	1	-5/+40
\| *	Fixed a va_list corruption in logv_error()	Clifford Wolf	2014-08-02	1	-4/+3
\| *	Be more conservative with printing decimal numbers in verilog backend	Clifford Wolf	2014-08-02	1	-2/+3
\| *	Improved verilog output for ordinary $mux cells	Clifford Wolf	2014-08-02	1	-3/+19
\| *	Bugfix in "techmap -extern"	Clifford Wolf	2014-08-02	2	-10/+17
\| *	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02	3	-8/+7
\| *	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	16	-37/+37
\| *	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	10	-44/+60
\| *	Limit size of log_signal buffer to 100 elements	Clifford Wolf	2014-08-02	2	-2/+9
\| *	Improvements in new RTLIL::IdString implementation	Clifford Wolf	2014-08-02	5	-33/+65
\| *	Fixed a performance bug in opt_reduce	Clifford Wolf	2014-08-02	1	-2/+6
\| *	Implemented new reference counting RTLIL::IdString	Clifford Wolf	2014-08-02	2	-15/+90
\| *	Fixed memory corruption related to id2cstr()	Clifford Wolf	2014-08-02	1	-2/+2
\| *	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	33	-261/+237
\| *	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	12	-32/+71
\| *	Added logfile hash to statistics footer	Clifford Wolf	2014-08-01	5	-45/+79
\| *	Replaced sha1 implementation	Clifford Wolf	2014-08-01	8	-283/+334
\| *	Added per-pass cpu usage statistics	Clifford Wolf	2014-08-01	4	-12/+86
\| *	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	9	-30/+170
\| *	Packed SigBit::data and SigBit::offset in a union	Clifford Wolf	2014-08-01	2	-10/+14
\| *	Consolidated hana test benches into fewer files	Clifford Wolf	2014-08-01	175	-1332/+1622
\| *	Added "test_autotb -n <num_iter>" option	Clifford Wolf	2014-08-01	2	-11/+32
\| *	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31	3	-12/+14
\| *	Various cleanups in Makefile, Renamed default configurations	Clifford Wolf	2014-07-31	1	-21/+12
\| *	Added compiler + compiler version + compiler flags to version string	Clifford Wolf	2014-07-31	1	-1/+2
\| *	Fixed build of verific bindings	Clifford Wolf	2014-07-31	1	-11/+11
\| *	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	46	-1059/+1086
\| *	Added "trace" command	Clifford Wolf	2014-07-31	4	-2/+103
\| *	Added RTLIL::Monitor	Clifford Wolf	2014-07-31	2	-96/+97
\| *	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	15	-44/+142