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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-03 20:19:50 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-03 20:22:33 +0200 |
| commit | c7f99be3be828606cafc7d35b3612f5344065736 (patch) | |
| tree | 64b7c48517c0be4809fa0cfb8a68621f8f2366d3 | |
| parent | 358bf70a2111d476d9d209f216fdd087356ec0d9 (diff) | |
| download | yosys-c7f99be3be828606cafc7d35b3612f5344065736.tar.gz yosys-c7f99be3be828606cafc7d35b3612f5344065736.tar.bz2 yosys-c7f99be3be828606cafc7d35b3612f5344065736.zip | |
Fixed "share" for memory read ports
| -rw-r--r-- | passes/sat/share.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 4484d6771..0c88b4d3c 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -419,6 +419,13 @@ struct ShareWorker return supercell; } + if (c1->type == "$memrd") + { + RTLIL::Cell *supercell = module->addCell(NEW_ID, c1); + module->connect(c2->getPort("\\DATA"), supercell->getPort("\\DATA")); + return supercell; + } + log_abort(); } |