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* Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-0635-290/+787
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| * Fix the other bison warning in ilang_parser.yClifford Wolf2019-05-061-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Bugfix in peepopt_shiftmul.pmgClifford Wolf2019-05-061-0/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #992 from bwidawsk/bison-fixClifford Wolf2019-05-061-1/+1
| |\ | | | | | | verilog_parser: Fix Bison warning
| | * verilog_parser: Fix Bison warningBen Widawsky2019-05-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of Bison 2.6, name-prefix is deprecated. This fixes frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated] %name-prefix "frontend_verilog_yy" For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html Compile tested only. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | Merge pull request #989 from YosysHQ/dave/abc_name_improveClifford Wolf2019-05-061-8/+21
| |\ \ | | | | | | | | ABC name recovery fixes
| | * | abc: Fix handling of postfixed names (e.g. for retiming)David Shah2019-05-041-4/+4
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | abc: Improve name recoveryDavid Shah2019-05-041-4/+17
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | Fix bug in "expose -input"Clifford Wolf2019-05-061-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Cleanups in opt_cleanClifford Wolf2019-05-061-47/+16
| | |/ | |/| | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-042-1/+5
| |\ \ | | |/ | |/| Add approximate support for SV "var" keyword
| | * Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-042-1/+5
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improve opt_clean handling of unused wiresClifford Wolf2019-05-041-10/+22
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add support for SVA "final" keywordClifford Wolf2019-05-042-1/+5
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Rename cells_map.v to prevent clash with ff_map.vEddie Hung2019-05-031-6/+8
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| * iverilog with simcells.v as wellEddie Hung2019-05-031-1/+2
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| * Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-0313-151/+509
| |\ | | | | | | Improve pmgen, Add "peepopt" pass with shift-mul pattern
| | * Update pmgen documentationClifford Wolf2019-05-031-6/+18
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Fix typoClifford Wolf2019-05-031-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Add peepopt_muldiv, fixes #930Clifford Wolf2019-04-306-1/+86
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * pmgen progressClifford Wolf2019-04-304-13/+27
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Run "peepopt" in generic "synth" pass and "synth_ice40"Clifford Wolf2019-04-302-0/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmgClifford Wolf2019-04-303-4/+6
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Progress in shiftmul peepopt patternClifford Wolf2019-04-301-3/+51
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Add "peepopt" skeletonClifford Wolf2019-04-295-1/+112
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Add pmgen support for multiple patterns in one matcherClifford Wolf2019-04-293-130/+188
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Support multiple pmg files (right now just concatenated together)Clifford Wolf2019-04-291-6/+30
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #984 from YosysHQ/eddie/fix_982Clifford Wolf2019-05-031-1/+2
| |\ \ | | | | | | | | dffinit to do nothing when (* init *) value is 1'bx
| | * | Revert "synth_xilinx to call dffinit with -noreinit"Eddie Hung2019-05-031-1/+1
| | | | | | | | | | | | | | | | This reverts commit 1f62dc9081feb4852b1848d01951f631853edb38.
| | * | If init is 1'bx, do not add to dict as per @cliffordwolfEddie Hung2019-05-031-1/+2
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| | * | Revert "dffinit -noreinit to silently continue when init value is 1'bx"Eddie Hung2019-05-031-12/+4
| | | | | | | | | | | | | | | | This reverts commit aa081f83c791b1d666214776aaf744a80ce6a690.
| | * | synth_xilinx to call dffinit with -noreinitEddie Hung2019-05-021-1/+1
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| | * | dffinit -noreinit to silently continue when init value is 1'bxEddie Hung2019-05-021-4/+12
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| * | | Merge pull request #976 from YosysHQ/clifford/fix974Clifford Wolf2019-05-033-0/+25
| |\ \ \ | | | | | | | | | | Fix width detection of memory access with bit slice
| | * | | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-012-0/+23
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | Fix width detection of memory access with bit slice, fixes #974Clifford Wolf2019-05-011-0/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Merge pull request #985 from YosysHQ/clifford/fix981Clifford Wolf2019-05-032-44/+81
| |\ \ \ \ | | | | | | | | | | | | Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires
| | * | | | Improve opt_expr and opt_clean handling of (partially) undriven and/or ↵Clifford Wolf2019-05-032-44/+81
| | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | unused wires, fixes #981 Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Fix typo in tests/svinterfaces/runone.shClifford Wolf2019-05-031-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Merge pull request #979 from jakobwenzel/svinterfacesTestcaseClifford Wolf2019-05-031-2/+2
| |\ \ \ \ | | |/ / / | |/| | | fail svinterfaces testcases on yosys error exit
| | * | | fail svinterfaces testcases on yosys error exitJakob Wenzel2019-05-021-2/+2
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| * | | Merge pull request #963 from YosysHQ/eddie/synth_xilinx_fineClifford Wolf2019-05-023-34/+30
| |\ \ \ | | | | | | | | | | Revert synth_xilinx 'fine' label more to how it used to be...
| | * | | Back to passing all xc7srl tests!Eddie Hung2019-05-011-5/+4
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| | * | | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fineEddie Hung2019-05-0122-190/+286
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| | * | | | WIPEddie Hung2019-04-281-36/+22
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| | * | | | Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-04-282-9/+12
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| | * | | | Revert synth_xilinx 'fine' label more to how it used to be...Eddie Hung2019-04-261-21/+40
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| * | | | | Merge pull request #978 from ucb-bar/fmtfirrtlEddie Hung2019-05-011-25/+25
| |\ \ \ \ \ | | |_|/ / / | |/| | | | Re-indent firrtl.cc:struct memory - no functional change.
| | * | | | Re-indent firrtl.cc:struct memory - no functional change.Jim Lawson2019-05-011-25/+25
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| * | | | | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-05-0121-176/+273
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