| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Actually, there might not be any harm in updating sigmap... | Eddie Hung | 2019-08-22 | 1 | -3/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add comment as per @cliffordwolf | Eddie Hung | 2019-08-22 | 1 | -0/+11 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add shregmap -tech xilinx test | Eddie Hung | 2019-08-22 | 1 | -0/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert "Try way that doesn't involve creating a new wire" | Eddie Hung | 2019-08-22 | 1 | -15/+10 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Try way that doesn't involve creating a new wire | Eddie Hung | 2019-08-22 | 1 | -10/+15 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If d_bit already in sigbit_chain_next, create extra wire | Eddie Hung | 2019-08-22 | 1 | -3/+6 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add doc | Eddie Hung | 2019-08-22 | 1 | -1/+14 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add copyright | Eddie Hung | 2019-08-22 | 1 | -0/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CHANGELOG entry | Eddie Hung | 2019-08-22 | 1 | -0/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove `shregmap -tech xilinx` additions | Eddie Hung | 2019-08-22 | 1 | -189/+8 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pmgen to also iterate over all module ports | Eddie Hung | 2019-08-22 | 1 | -2/+4 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove output_bits | Eddie Hung | 2019-08-22 | 2 | -16/+7 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Forgot to set ud_variable.minlen | Eddie Hung | 2019-08-22 | 1 | -0/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not run xilinx_srl_pm in fixed loop | Eddie Hung | 2019-08-22 | 1 | -28/+24 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-22 | 19 | -102/+1046 | |
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| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-22 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reuse var | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert "Trim shiftx_width when upper bits are 1'bx" | Eddie Hung | 2019-08-21 | 1 | -6/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | opt_expr to trim A port of $shiftx if Y_WIDTH == 1 | Eddie Hung | 2019-08-21 | 1 | -0/+17 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trim shiftx_width when upper bits are 1'bx | Eddie Hung | 2019-08-21 | 1 | -1/+6 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add comment | Eddie Hung | 2019-08-21 | 1 | -0/+4 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add variable length support to xilinx_srl | Eddie Hung | 2019-08-21 | 3 | -18/+167 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename pattern to fixed | Eddie Hung | 2019-08-21 | 2 | -10/+10 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | attribute -> attr | Eddie Hung | 2019-08-21 | 1 | -4/+4 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use Cell::has_keep_attribute() | Eddie Hung | 2019-08-21 | 1 | -4/+4 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | abc9 to perform new 'map_ffs' before 'map_luts' | Eddie Hung | 2019-08-21 | 1 | -3/+18 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xilinx_srl to support FDRE and FDRE_1 | Eddie Hung | 2019-08-21 | 2 | -10/+73 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix polarity of EN_POL | Eddie Hung | 2019-08-21 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CLKPOL == 0 | Eddie Hung | 2019-08-21 | 1 | -0/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reject if not minlen from inside pattern matcher | Eddie Hung | 2019-08-21 | 2 | -8/+11 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Get wire via SigBit | Eddie Hung | 2019-08-21 | 1 | -4/+4 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Respect \keep on cells or wires | Eddie Hung | 2019-08-21 | 1 | -2/+10 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl | Eddie Hung | 2019-08-21 | 2 | -0/+17 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add init support | Eddie Hung | 2019-08-21 | 2 | -3/+12 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix spacing | Eddie Hung | 2019-08-21 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initial progress on xilinx_srl | Eddie Hung | 2019-08-21 | 3 | -0/+213 | |
| | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Format `-pwires` | Eddie Hung | 2019-08-30 | 1 | -1/+1 | |
| | |_|_|_|_|_|_|_|/ / / / / / / / / / / / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1343 from whitequark/diamond-ffs | David Shah | 2019-08-30 | 7 | -106/+147 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|_|_|/ / / / / / / / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ecp5: Add simulation equivalence check for Diamond FF implementations | David Shah | 2019-08-30 | 3 | -0/+87 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives. | whitequark | 2019-08-30 | 5 | -95/+60 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ecp5: allow (and enable by default) GSR on FD/IFS/OFS primitives. | whitequark | 2019-08-30 | 1 | -35/+20 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ecp5: add missing FD primitives. | whitequark | 2019-08-30 | 2 | -72/+76 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ecp5: fix CEMUX on IFS/OFS primitives. | whitequark | 2019-08-30 | 2 | -18/+18 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1337 from YosysHQ/eddie/fix_carry_wrapper | Eddie Hung | 2019-08-29 | 7 | -27/+71 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|_|/ / / / / / / / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename boxes too | Eddie Hung | 2019-08-29 | 3 | -3/+3 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add run-test.sh too | Eddie Hung | 2019-08-28 | 1 | -0/+20 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not overwrite LUT param | Eddie Hung | 2019-08-28 | 1 | -1/+0 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SB_CARRY to ice40_opt test | Eddie Hung | 2019-08-28 | 1 | -3/+5 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ice40_opt test | Eddie Hung | 2019-08-28 | 1 | -0/+24 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trailing comma | Eddie Hung | 2019-08-28 | 1 | -1/+1 | |
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index : iCE40/yosys | |
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