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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 10:27:07 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-30 10:27:07 -0700 |
| commit | 9c4e1c6a8fc47f44011f1f75e9493a1bc2de520d (patch) | |
| tree | 4b907cceaf61c092ddcfc99f684f9bb2e40642a1 | |
| parent | a94a8f3e4030b3a4697c2201ef65c83b01f25ffb (diff) | |
| download | yosys-9c4e1c6a8fc47f44011f1f75e9493a1bc2de520d.tar.gz yosys-9c4e1c6a8fc47f44011f1f75e9493a1bc2de520d.tar.bz2 yosys-9c4e1c6a8fc47f44011f1f75e9493a1bc2de520d.zip | |
Format `-pwires`
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -330,7 +330,7 @@ Verilog Attributes and non-standard features - The ``parameter`` and ``localparam`` attributes are used to mark wires that represent module parameters or localparams (when the HDL front-end - is run in -pwires mode). + is run in ``-pwires`` mode). - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` |