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* | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-04-261-1/+0
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* | | | | | | | | | | | | | | | | | Remove split_shiftx callEddie Hung2019-04-261-4/+1
* | | | | | | | | | | | | | | | | | Revert "Merge branch 'eddie/split_shiftx' into xc7mux"Eddie Hung2019-04-269-158/+14
* | | | | | | | | | | | | | | | | | Missing newlineEddie Hung2019-04-261-1/+1
* | | | | | | | | | | | | | | | | | Add -undef option to equiv_opt, passed to equiv_inductEddie Hung2019-04-261-3/+16
* | | | | | | | | | | | | | | | | | Actually use pm.st.shiftxBEddie Hung2019-04-252-3/+6
* | | | | | | | | | | | | | | | | | Cleanup supersededEddie Hung2019-04-251-11/+1
* | | | | | | | | | | | | | | | | | bitblast_shiftx -> split_shiftxEddie Hung2019-04-251-2/+2
* | | | | | | | | | | | | | | | | | Fix for when B_WIDTH has trailing zeroesEddie Hung2019-04-251-5/+9
* | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/split_shiftx' into xc7muxEddie Hung2019-04-254-16/+157
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| * | | | | | | | | | | | | | | | | | In order to indicate a failed pattern, blacklist?Eddie Hung2019-04-252-15/+16
| * | | | | | | | | | | | | | | | | | Add testEddie Hung2019-04-252-0/+139
| * | | | | | | | | | | | | | | | | | Elaborate on help messageEddie Hung2019-04-251-1/+2
* | | | | | | | | | | | | | | | | | | Merge branch 'eddie/split_shiftx' into xc7muxEddie Hung2019-04-259-14/+149
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| * | | | | | | | | | | | | | | | | | Add split_shiftx commandEddie Hung2019-04-252-0/+134
| * | | | | | | | | | | | | | | | | | Make pmgen support files more genericEddie Hung2019-04-252-6/+9
* | | | | | | | | | | | | | | | | | | synth_xilinx to call bitblast_shiftxEddie Hung2019-04-251-1/+4
* | | | | | | | | | | | | | | | | | | Remove topo sort no-loop assertion, with testEddie Hung2019-04-244-14/+76
* | | | | | | | | | | | | | | | | | | Add -nocarry option to synth_xilinxEddie Hung2019-04-241-5/+14
* | | | | | | | | | | | | | | | | | | Fix abc9 with (* keep *) wiresEddie Hung2019-04-232-6/+52
* | | | | | | | | | | | | | | | | | | Refactor into AigerReader::post_process()Eddie Hung2019-04-232-249/+161
* | | | | | | | | | | | | | | | | | | TweakEddie Hung2019-04-221-1/+1
* | | | | | | | | | | | | | | | | | | Fix for A_WIDTH == 2 but B_WIDTH==3Eddie Hung2019-04-221-1/+1
* | | | | | | | | | | | | | | | | | | Trim A_WIDTH by Y_WIDTH-1Eddie Hung2019-04-221-1/+1
* | | | | | | | | | | | | | | | | | | Add commentEddie Hung2019-04-221-0/+3
* | | | | | | | | | | | | | | | | | | Fix for mux_case_* mappingsEddie Hung2019-04-221-17/+9
* | | | | | | | | | | | | | | | | | | Fix for non-pow2 width muxesEddie Hung2019-04-221-9/+18
* | | | | | | | | | | | | | | | | | | Add synth_xilinx -nomux optionEddie Hung2019-04-222-4/+18
* | | | | | | | | | | | | | | | | | | Cleanup, call pmux2shiftx even without -nosrlEddie Hung2019-04-226-45/+30
* | | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7muxEddie Hung2019-04-2231-283/+953
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* \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/xc7srl' into xc7muxEddie Hung2019-04-2277-348/+4702
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* | | | | | | | | | | | | | | | | | | | | Add MUXCY and XORCY to cells_box.vEddie Hung2019-04-162-0/+15
* | | | | | | | | | | | | | | | | | | | | Fix wire numberingEddie Hung2019-04-161-1/+2
* | | | | | | | | | | | | | | | | | | | | Do not put constants into output_bitsEddie Hung2019-04-161-2/+2
* | | | | | | | | | | | | | | | | | | | | Remove write_verilog callEddie Hung2019-04-161-1/+1
* | | | | | | | | | | | | | | | | | | | | Fix spacingEddie Hung2019-04-162-2/+2
* | | | | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7muxEddie Hung2019-04-162-3/+1
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* | | | | | | | | | | | | | | | | | | | | | NULL check before useEddie Hung2019-04-161-1/+1
* | | | | | | | | | | | | | | | | | | | | | WIP for box supportEddie Hung2019-04-161-36/+93
* | | | | | | | | | | | | | | | | | | | | | ABC to read_box before reading netlistEddie Hung2019-04-161-1/+3
* | | | | | | | | | | | | | | | | | | | | | Make cells.box whiteboxes not blackboxesEddie Hung2019-04-161-2/+2
* | | | | | | | | | | | | | | | | | | | | | read_verilog cells_box.v before techmapEddie Hung2019-04-161-1/+1
* | | | | | | | | | | | | | | | | | | | | | synth_xilinx: before abc read +/xilinx/cells_box.vEddie Hung2019-04-161-0/+1
* | | | | | | | | | | | | | | | | | | | | | Add +/xilinx/cells_box.v containing models for ABC boxesEddie Hung2019-04-162-0/+11
* | | | | | | | | | | | | | | | | | | | | | For 'stat' do not count modules with abc_box_idEddie Hung2019-04-161-0/+3
* | | | | | | | | | | | | | | | | | | | | | Do not call abc on modules with abc_box_id attrEddie Hung2019-04-161-0/+3
* | | | | | | | | | | | | | | | | | | | | | Revert "Add abc_box_id attribute to MUXF7/F8 cells"Eddie Hung2019-04-161-2/+0
* | | | | | | | | | | | | | | | | | | | | | Use abc_box_idEddie Hung2019-04-151-2/+1
* | | | | | | | | | | | | | | | | | | | | | Check abc_box_id attrEddie Hung2019-04-151-1/+16
* | | | | | | | | | | | | | | | | | | | | | Add abc_box_id attribute to MUXF7/F8 cellsEddie Hung2019-04-151-0/+2