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* bugpoint: Don't remove modules or cells while iterating over them.Marcelina Kościelnicka2020-04-221-4/+14
* intel_alm: Documentation improvementsDan Ravensloft2020-04-213-14/+127
* write_json: dump default parameter valuesMarcelina Kościelnicka2020-04-211-0/+10
* Use default parameter value in getParamMarcelina Kościelnicka2020-04-212-4/+13
* hierarchy: Convert positional parameters to named.Marcelina Kościelnicka2020-04-212-3/+50
* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-216-9/+27
* idict: Make iterator go forward.Marcelina Kościelnicka2020-04-211-5/+19
* Merge pull request #1971 from YosysHQ/claire/edifkeepClaire Wolf2020-04-211-14/+108
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| * Improve net priorities in EDIF back-endClaire Wolf2020-04-211-0/+64
| * Ignore conflicting keep attributes, unless asked not to. Fixes #1733Claire Wolf2020-04-201-14/+44
* | Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-2117-15/+1431
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| * \ Merge pull request #1975 from dh73/claire/bitselwriteEddie Hung2020-04-2013-0/+1224
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| | * | Remove '-ignore_unknown_cells' option from 'sat'Eddie Hung2020-04-201-6/+6
| | * | Simplify test case scriptEddie Hung2020-04-201-30/+17
| | * | Remove ununsed filesEddie Hung2020-04-205-83/+0
| | * | Modifications of tests as per Eddie's requestdiego2020-04-2015-78/+1237
| | * | Wrong fixed valuediego2020-04-171-1/+1
| | * | Adding tests for dynamic part select optimisationdiego2020-04-167-0/+161
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| * | Make mask-and-shift the default for bitselwriteClaire Wolf2020-04-161-1/+1
| * | Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-164-4/+144
| * | Improved rewrite code for writing to bit slice (disabled for now)Claire Wolf2020-04-151-12/+64
* | | Merge pull request #1961 from whitequark/paramod-original-namewhitequark2020-04-213-11/+7
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| * | | ast, rpc: record original name of $paramod\* as \hdlname attribute.whitequark2020-04-183-11/+7
* | | | tests: remove write_ilangEddie Hung2020-04-202-3/+0
* | | | Merge pull request #1972 from YosysHQ/eddie/bug1970Eddie Hung2020-04-202-16/+52
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| * | | abc9: -prep_lut to be more robustEddie Hung2020-04-201-16/+33
| * | | abc9: add testcase reduced from #1970Eddie Hung2020-04-201-0/+19
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* | | Merge pull request #1964 from YosysHQ/claire/sformatfClaire Wolf2020-04-201-8/+38
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| * | | Extend support for format strings in Verilog front-endClaire Wolf2020-04-181-8/+38
* | | | Merge pull request #1967 from whitequark/cxxrtl-blackbox-attributeswhitequark2020-04-192-49/+57
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| * | | cxxrtl: provide attributes to black box factories, too.whitequark2020-04-192-49/+57
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* | | Merge pull request #1963 from whitequark/cxxrtl-blackboxeswhitequark2020-04-182-198/+637
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| * | | cxxrtl: add templated black box support.whitequark2020-04-181-16/+193
| * | | cxxrtl: make eval() and commit() inline in blackboxes.whitequark2020-04-181-82/+103
| * | | cxxrtl: add simple black box support.whitequark2020-04-182-70/+311
| * | | cxxrtl: use ID::X instead of ID(X). NFC.whitequark2020-04-181-107/+107
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* | | Merge pull request #1955 from whitequark/cxxrtl-sync_alwayswhitequark2020-04-171-3/+13
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| * | | cxxrtl: correctly handle `sync always` rules.whitequark2020-04-171-3/+13
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* | | Merge pull request #1952 from boqwxp/add_edge_locationwhitequark2020-04-171-0/+3
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| * | Set Verilog source location for explicit blocks (`begin` ... `end`).Alberto Gonzalez2020-04-171-0/+1
| * | Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` no...Alberto Gonzalez2020-04-171-0/+2
* | | Merge pull request #1954 from YosysHQ/dave/fix-stdout-conflictwhitequark2020-04-171-3/+3
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| * | | qbfsat: Fix illegal use of 'stdout' identifierDavid Shah2020-04-171-3/+3
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* | | Merge pull request #1951 from whitequark/rtlil-string_attributewhitequark2020-04-172-19/+33
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| * | rtlil: add AttrObject::has_attribute.whitequark2020-04-162-0/+7
| * | rtlil: add AttrObject::{get,set}_string_attribute.whitequark2020-04-162-19/+26
* | | Merge pull request #1898 from boqwxp/locationswhitequark2020-04-171-0/+3
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| * | | Add location information to `AST_CONSTANT` nodes.Alberto Gonzalez2020-04-161-0/+3
* | | | Merge pull request #1864 from boqwxp/cleanup_techmap_abcwhitequark2020-04-171-99/+80
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| * | | | Simplify `passes/techmap/abc.cc` and remove superfluous `RTLIL::SigSpec` cons...Alberto Gonzalez2020-04-141-132/+49