iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
...
\| * \| \| \| \| \| \| \| \| \| \|	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2019-02-15	3	-44/+47
\| \|\ \ \ \ \ \ \ \ \ \ \
\| * \ \ \ \ \ \ \ \ \ \ \	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2019-02-11	109	-413/+3479
\| \|\ \ \ \ \ \ \ \ \ \ \ \
\| * \| \| \| \| \| \| \| \| \| \| \| \|	Fix botched merge in CHANGELOG	Jim Lawson	2018-12-18	1	-1/+0
\| * \| \| \| \| \| \| \| \| \| \| \| \|	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2018-12-18	128	-636/+8336
\| \|\ \ \ \ \ \ \ \ \ \ \ \ \
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Improve Verific importer blackbox handling	Clifford Wolf	2018-10-08	1	-2/+14
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Add "write_edif -attrprop"	Clifford Wolf	2018-10-08	1	-11/+28
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix compiler warning in verific.cc	Clifford Wolf	2018-10-08	1	-0/+2
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix misspelling in issue_template.md	Tim Ansell	2018-10-08	1	-1/+1
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix IdString M in setup_stdcells()	Adrian Wheeldon	2018-10-08	1	-1/+1
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Add inout ports to cells_xtra.v	Clifford Wolf	2018-10-08	2	-2/+14
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	xilinx: Adding missing inout IO port to IOBUF	Tim Ansell	2018-10-08	1	-0/+1
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix for issue 594.	Tom Verbeure	2018-10-08	1	-1/+2
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Add read_verilog $changed support	Dan Gisselquist	2018-10-08	1	-1/+4
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	ecp5: Don't map ROMs to DRAM	David Shah	2018-10-08	1	-0/+1
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix handling of $past 2nd argument in read_verilog	Clifford Wolf	2018-10-08	1	-1/+1
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Update to v2 YosysVS template	Clifford Wolf	2018-10-08	1	-4/+4
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Add "read_verilog -noassert -noassume -assert-assumes"	Clifford Wolf	2018-10-08	3	-6/+49
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Added support for ommited "parameter" in Verilog-2001 style parameter decl in...	Clifford Wolf	2018-10-08	1	-3/+9
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Update CHANGELOG	Clifford Wolf	2018-10-08	1	-2/+35
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	added prefix to FDirection constants, fixing windows build	Miodrag Milanovic	2018-10-08	1	-11/+11
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Update CHANGLELOG	Clifford Wolf	2018-10-08	1	-5/+27
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Update Changelog	Clifford Wolf	2018-10-08	1	-1/+54
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix Cygwin build and document needed packages	Miodrag Milanovic	2018-10-08	3	-1/+14
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Fixed typo in "verilog_write" help message	acw1251	2018-10-08	2	-5/+5
\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2018-09-17	11	-14/+78
\| \|\ \ \ \ \ \ \ \ \ \ \ \ \ \
\| * \ \ \ \ \ \ \ \ \ \ \ \ \ \	Merge pull request #4 from YosysHQ/master	Jim Lawson	2018-08-28	3	-23/+112
\| \|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \
* \| \ \ \ \ \ \ \ \ \ \ \ \ \ \ \	Merge pull request #1024 from YosysHQ/eddie/fix_Wmissing_braces	Eddie Hung	2019-05-21	1	-5/+9
\|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \| \|_\|_\|_\|_\|_\|_\|_\|_\|_\|_\|_\|_\|_\|_\|_\|/ \|/\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Rename label	Eddie Hung	2019-05-21	1	-6/+5
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Try again	Eddie Hung	2019-05-21	1	-4/+10
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix warning	Eddie Hung	2019-05-21	1	-3/+2
\|/ / / / / / / / / / / / / / / /
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1017 from Kmanfi/bigger_verilog_files	Clifford Wolf	2019-05-18	1	-1/+1
\|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Read bigger Verilog files.	Kaj Tuomi	2019-05-18	1	-1/+1
\|/ / / / / / / / / / / / / / / /
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1013 from antmicro/parameter_attributes	Clifford Wolf	2019-05-16	3	-2/+24
\|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Added tests for Verilog frontent for attributes on parameters and localparams	Maciej Kurc	2019-05-16	2	-0/+22
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Added support for parsing attributes on parameters in Verilog frontent. Conte...	Maciej Kurc	2019-05-16	1	-2/+2
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1012 from YosysHQ/clifford/sigspecrw	Clifford Wolf	2019-05-15	3	-17/+92
\|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Improvements in opt_clean	Clifford Wolf	2019-05-15	1	-10/+10
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Add rewrite_sigspecs2, Improve remove() wires	Clifford Wolf	2019-05-15	2	-7/+82
\|/ / / / / / / / / / / / / / / / /
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Do not leak file descriptors in cover.cc	Clifford Wolf	2019-05-15	1	-5/+6
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1011 from hzeller/fix-constructing-string-from-int	Clifford Wolf	2019-05-15	2	-2/+3
\|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix two instances of integer-assignment to string.	Henner Zeller	2019-05-14	2	-2/+3
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1010 from hzeller/yacc-self-contained	Clifford Wolf	2019-05-15	2	-2/+18
\|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Make the generated *.tab.hh include all the headers needed to define the union.	Henner Zeller	2019-05-14	2	-2/+18
\| \|/ / / / / / / / / / / / / / / / /
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1008 from thasti/fix_libyosys_build	Clifford Wolf	2019-05-15	1	-5/+6
\|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \| \|_\|/ / / / / / / / / / / / / / / / \|/\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	extract python prefix to allow overriding	Stefan Biereigel	2019-05-14	1	-1/+2
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	remove ldconfig call	Stefan Biereigel	2019-05-14	1	-1/+0
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	add mkdir for libyosys target, explicitly copy to target folder	Stefan Biereigel	2019-05-14	1	-3/+4
\| \|/ / / / / / / / / / / / / / / /
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1005 from smunaut/ice40_hfosc_trim	David Shah	2019-05-15	1	-0/+11
\|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \| \|/ / / / / / / / / / / / / / / / \|/\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC	Sylvain Munaut	2019-05-13	1	-0/+11
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	bugpoint: check for -script option.	whitequark	2019-05-14	1	-0/+3
\|/ / / / / / / / / / / / / / / /