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| author | Maciej Kurc <mkurc@antmicro.com> | 2019-05-16 12:44:16 +0200 |
|---|---|---|
| committer | Maciej Kurc <mkurc@antmicro.com> | 2019-05-16 12:44:16 +0200 |
| commit | ce4a0954bc896eedfc2d87e2c9d2b40f42a101db (patch) | |
| tree | b5bc8a5bbbfd930a9b3a73f862032f1b84935c6c | |
| parent | 3ef88ffbb2409450d5921938b2b938c4c007e091 (diff) | |
| download | yosys-ce4a0954bc896eedfc2d87e2c9d2b40f42a101db.tar.gz yosys-ce4a0954bc896eedfc2d87e2c9d2b40f42a101db.tar.bz2 yosys-ce4a0954bc896eedfc2d87e2c9d2b40f42a101db.zip | |
Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index d23009e60..ce1eb31d8 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1193,7 +1193,7 @@ param_range: }; param_decl: - TOK_PARAMETER { + attr TOK_PARAMETER { astbuf1 = new AstNode(AST_PARAMETER); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); } param_signed param_integer param_real param_range param_decl_list ';' { @@ -1201,7 +1201,7 @@ param_decl: }; localparam_decl: - TOK_LOCALPARAM { + attr TOK_LOCALPARAM { astbuf1 = new AstNode(AST_LOCALPARAM); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); } param_signed param_integer param_real param_range param_decl_list ';' { |