aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* opt_lut: reflect changes in sigmap.whitequark2019-01-021-0/+2
| | | | Otherwise, some LUTs will be missed during elimination.
* opt_lut: use a worklist, and revisit cells affected by elimination.whitequark2019-01-021-3/+10
|
* opt_lut: count eliminated cells, and set opt.did_something for them.whitequark2019-01-021-6/+20
|
* Merge pull request #768 from whitequark/opt_lut_elimClifford Wolf2019-01-014-0/+104
|\ | | | | opt_lut: eliminate LUTs evaluating to constants or inputs
| * opt_lut: eliminate LUTs evaluating to constants or inputs.whitequark2018-12-314-0/+104
|/
* Fix handling of (* keep *) wires in wreduceClifford Wolf2018-12-311-1/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #766 from Icenowy/anlogic-latchesClifford Wolf2018-12-311-0/+12
|\ | | | | anlogic: add latch cells
| * anlogic: add latch cellsIcenowy Zheng2018-12-251-0/+12
| | | | | | | | | | | | | | Add latch cells to Anlogic cells replacement library by copying other FPGAs' latch code to it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | Fix 7 instances of add_share_file to add_gen_share_fileLarry Doolittle2018-12-291-8/+8
| | | | | | | | in techlibs/ecp5/Makefile.inc to permit out-of-tree builds
* | Squelch a little more trailing whitespaceLarry Doolittle2018-12-292-4/+4
| |
* | Merge pull request #761 from whitequark/proc_clean_partialClifford Wolf2018-12-233-10/+42
|\ \ | | | | | | proc_clean: remove any empty cases, if possible to do safely
| * | proc_clean: remove any empty cases if all cases use all-def compare.whitequark2018-12-233-6/+42
| | |
| * | proc_clean: remove any empty cases at the end of the switch.whitequark2018-12-221-7/+3
| | | | | | | | | | | | Previously, only completely empty switches were removed.
* | | Add "read_ilang -[no]overwrite"Clifford Wolf2018-12-233-4/+54
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge branch 'master' of github.com:YosysHQ/yosysClifford Wolf2018-12-237-22/+58
|\ \ \
| * \ \ Merge pull request #757 from whitequark/manual_memClifford Wolf2018-12-222-10/+37
| |\ \ \ | | |/ / | |/| | manual: document $meminit cell and memory_* passes
| | * | manual: make description of $meminit ports match reality.whitequark2018-12-211-3/+15
| | | |
| | * | manual: fix typos.whitequark2018-12-201-2/+2
| | | |
| | * | manual: document $meminit cell and memory_* passes.whitequark2018-12-202-8/+23
| | | |
| * | | Merge pull request #758 from whitequark/tcl_script_argsClifford Wolf2018-12-211-7/+18
| |\ \ \ | | | | | | | | | | tcl: add support for passing arguments to scripts
| | * | | tcl: add support for passing arguments to scripts.whitequark2018-12-201-7/+18
| | | |/ | | |/|
| * | | Merge pull request #759 from whitequark/memory_collect_init_xClifford Wolf2018-12-211-3/+0
| |\ \ \ | | |/ / | |/| | memory_collect: do not truncate 'x from \INIT
| | * | memory_collect: do not truncate 'x from \INIT.whitequark2018-12-211-3/+0
| |/ / | | | | | | | | | | | | | | | | | | The semantics of an RTLIL constant that has less bits than its declared bit width is zero padding. Therefore, if the output of memory_collect will be used for simulation, truncating 'x from the end of \INIT will produce incorrect simulation results.
| * | Merge pull request #752 from Icenowy/anlogic-lut-costClifford Wolf2018-12-191-1/+1
| |\ \ | | | | | | | | Anlogic: let LUT5/6 have more cost than LUT4-
| | * | Anlogic: let LUT5/6 have more cost than LUT4-Icenowy Zheng2018-12-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s. So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost 2x resource of a LUT5. Change the -lut parameter passed to the abc command to pass this cost info to the ABC process. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
| * | | Merge pull request #753 from Icenowy/anlogic-makefile-fixClifford Wolf2018-12-191-0/+1
| |\ \ \ | | | | | | | | | | anlogic: fix Makefile.inc
| | * | | anlogic: fix Makefile.incIcenowy Zheng2018-12-191-0/+1
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the addition of DRAM inferring support, the installation of eagle_bb.v is accidentally removed. Fix this issue. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
| * | | Merge pull request #749 from Icenowy/anlogic-dram-fixClifford Wolf2018-12-191-1/+1
| |\ \ \ | | | | | | | | | | anlogic: fix dbits of Anlogic Eagle DRAM16X4
| | * | | anlogic: fix dbits of Anlogic Eagle DRAM16X4Icenowy Zheng2018-12-181-1/+1
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM bits. Fix the dbits number in the RAM configuration. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | / / Minor style fixesClifford Wolf2018-12-182-1/+1
|/ / / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #748 from makaimann/add-btor-opsClifford Wolf2018-12-182-2/+38
|\ \ \ | | | | | | | | Add btor ops for $mul, $div, $mod and $concat
| * | | Add btor ops for $mul, $div, $mod and $concatmakaimann2018-12-172-2/+38
| |/ /
* | | Merge pull request #751 from daveshah1/fix_589Clifford Wolf2018-12-181-1/+1
|\ \ \ | | | | | | | | memory_dff: Fix typo when checking init value
| * | | memory_dff: Fix typo when checking init valueDavid Shah2018-12-181-1/+1
|/ / / | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | | Fix segfault in AST simplifyClifford Wolf2018-12-181-0/+5
| | | | | | | | | | | | | | | | | | (as proposed by Dan Gisselquist) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Improve src tagging (using names and attrs) of cells and wires in verific ↵Clifford Wolf2018-12-182-99/+160
|/ / | | | | | | | | | | front-end Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #746 from Icenowy/anlogic-dramClifford Wolf2018-12-175-1/+355
|\ \ | |/ |/| Support for DRAM inferring on Anlogic FPGAs
| * anlogic: add support for Eagle Distributed RAMIcenowy Zheng2018-12-174-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | The MSLICEs on the Eagle series of FPGA can be configured as Distributed RAM. Enable to synthesis to DRAM. As the Anlogic software suite doesn't support any 'bx to exist in the initializtion data of DRAM, do not enable the initialization support of the inferred DRAM. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
| * Revert "Leave only real black box cells"Icenowy Zheng2018-12-171-0/+312
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 43030db5fff285de85096aaf5578b0548659f6b7. For a synthesis tool, generating EG_LOGIC cells are a good choice, as they can be furtherly optimized when PnR, although sometimes EG_LOGIC is not as blackbox as EG_PHY cells (because the latter is more close to the hardware implementation). Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | Merge pull request #742 from whitequark/changelogClifford Wolf2018-12-171-0/+7
|\ \ | | | | | | Update CHANGELOG to mention my improvements
| * | Update CHANGELOG.whitequark2018-12-161-0/+7
| | |
* | | Merge pull request #741 from whitequark/ilang_slice_sigspecClifford Wolf2018-12-171-10/+6
|\ \ \ | | | | | | | | read_ilang: allow slicing all sigspecs, not just wires
| * | | read_ilang: allow slicing sigspecs.whitequark2018-12-161-10/+6
| |/ /
* | | Merge pull request #744 from whitequark/write_verilog_$shiftClifford Wolf2018-12-171-0/+29
|\ \ \ | |_|/ |/| | write_verilog: handle the $shift cell
| * | write_verilog: handle the $shift cell.whitequark2018-12-161-0/+29
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation corresponds to the following Verilog, which is lifted straight from simlib.v: module \\$shift (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 0; parameter B_WIDTH = 0; parameter Y_WIDTH = 0; input [A_WIDTH-1:0] A; input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; generate if (B_SIGNED) begin:BLOCK1 assign Y = $signed(B) < 0 ? A << -B : A >> B; end else begin:BLOCK2 assign Y = A >> B; end endgenerate endmodule
* | Merge pull request #745 from YosysHQ/revert-714-abc_preserve_namingClifford Wolf2018-12-161-51/+29
|\ \ | |/ |/| Revert "Proof-of-concept: preserve naming through ABC using dress"
| * Revert "Proof-of-concept: preserve naming through ABC using dress"Clifford Wolf2018-12-161-51/+29
|/
* Merge pull request #736 from whitequark/select_assert_listClifford Wolf2018-12-162-9/+51
|\ | | | | select: print selection if a -assert-* flag causes an error
| * select: print selection if a -assert-* flag causes an error.whitequark2018-12-161-8/+50
| |
| * write_verilog: add a missing newline.whitequark2018-12-161-1/+1
| |
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-30 19:35:46 +0000