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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-21 17:39:52 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-21 17:39:52 +0100 |
| commit | 29a82acb2e2f5c7f6417dcf3ebb6597afae4a789 (patch) | |
| tree | 31804c863f66c2231db22f99855f02487bbeb2fa | |
| parent | 93d44bb9a613b46a80642b8ce71295db18fadbc5 (diff) | |
| parent | 0c318e7db513bed1844f594ae780f854ed08e18f (diff) | |
| download | yosys-29a82acb2e2f5c7f6417dcf3ebb6597afae4a789.tar.gz yosys-29a82acb2e2f5c7f6417dcf3ebb6597afae4a789.tar.bz2 yosys-29a82acb2e2f5c7f6417dcf3ebb6597afae4a789.zip | |
Merge pull request #759 from whitequark/memory_collect_init_x
memory_collect: do not truncate 'x from \INIT
| -rw-r--r-- | passes/memory/memory_collect.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 70d98713c..369fcc84e 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -184,9 +184,6 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) mem->parameters["\\OFFSET"] = Const(memory->start_offset); mem->parameters["\\SIZE"] = Const(memory->size); mem->parameters["\\ABITS"] = Const(addr_bits); - - while (GetSize(init_data) > 1 && init_data.bits.back() == State::Sx && init_data.bits[GetSize(init_data)-2] == State::Sx) - init_data.bits.pop_back(); mem->parameters["\\INIT"] = init_data; log_assert(sig_wr_clk.size() == wr_ports); |