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* Add "wreduce -keepdc", fixes #1016Clifford Wolf2019-05-202-3/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1017 from Kmanfi/bigger_verilog_filesClifford Wolf2019-05-181-1/+1
|\ | | | | Read bigger Verilog files.
| * Read bigger Verilog files.Kaj Tuomi2019-05-181-1/+1
|/ | | | Hit parser limit with 3M gate design. This commit fix it.
* Merge pull request #1013 from antmicro/parameter_attributesClifford Wolf2019-05-163-2/+24
|\ | | | | Support for attributes on parameters and localparams for Verilog frontend
| * Added tests for Verilog frontent for attributes on parameters and localparamsMaciej Kurc2019-05-162-0/+22
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added support for parsing attributes on parameters in Verilog frontent. ↵Maciej Kurc2019-05-161-2/+2
| | | | | | | | | | | | Content of those attributes is ignored. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | Merge pull request #1012 from YosysHQ/clifford/sigspecrwClifford Wolf2019-05-153-17/+92
|\ \ | | | | | | Another rounds of opt_clean improvements
| * | Improvements in opt_cleanClifford Wolf2019-05-151-10/+10
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add rewrite_sigspecs2, Improve remove() wiresClifford Wolf2019-05-152-7/+82
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Do not leak file descriptors in cover.ccClifford Wolf2019-05-151-5/+6
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #1011 from hzeller/fix-constructing-string-from-intClifford Wolf2019-05-152-2/+3
|\ \ | | | | | | Fix two instances of integer-assignment to string.
| * | Fix two instances of integer-assignment to string.Henner Zeller2019-05-142-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | o In cover.cc, the int-result of mkstemps() was assigned to a string and silently interpreted as a single-character filename with a funny value. Fix with the intent: assign the filename. o in libparse.cc, an int was assigned to a string, but depending on visible constructors, this is ambiguous. Explicitly cast this to a char.
* | | Merge pull request #1010 from hzeller/yacc-self-containedClifford Wolf2019-05-152-2/+18
|\ \ \ | | | | | | | | Make the generated *.tab.hh include all the headers needed
| * | | Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-142-2/+18
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* | | Merge pull request #1008 from thasti/fix_libyosys_buildClifford Wolf2019-05-151-5/+6
|\ \ \ | |_|/ |/| | Create $(LIBDIR) to fix broken build in isolated environments
| * | extract python prefix to allow overridingStefan Biereigel2019-05-141-1/+2
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| * | remove ldconfig callStefan Biereigel2019-05-141-1/+0
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| * | add mkdir for libyosys target, explicitly copy to target folderStefan Biereigel2019-05-141-3/+4
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* | Merge pull request #1005 from smunaut/ice40_hfosc_trimDavid Shah2019-05-151-0/+11
|\ \ | |/ |/| ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC
| * ice40/cells_sim.v: Add support for TRIM input to SB_HFOSCSylvain Munaut2019-05-131-0/+11
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | bugpoint: check for -script option.whitequark2019-05-141-0/+3
|/ | | | Fixes #925.
* Merge pull request #1004 from YosysHQ/clifford/fix1002Clifford Wolf2019-05-121-3/+11
|\ | | | | Fix handling of glob_abort_cnt in opt_muxtree
| * Fix handling of glob_abort_cnt in opt_muxtree, fixes #1002Clifford Wolf2019-05-121-3/+11
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1003 from makaimann/zinit-allClifford Wolf2019-05-111-1/+1
|\ | | | | Zinit option '-singleton' -> '-all'
| * Zinit option '-singleton' -> '-all'Makai Mann2019-05-101-1/+1
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* | Add "fmcombine -initeq -anyeq"Clifford Wolf2019-05-111-3/+38
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "stat -tech xilinx"Clifford Wolf2019-05-112-4/+74
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1000 from bwidawsk/synth-formatClifford Wolf2019-05-092-222/+224
|\ | | | | Add clang format, and use on intel_synth (v2)
| * Fix formatting for synth_intel.ccBen Widawsky2019-05-091-222/+211
| | | | | | | | | | | | This is realized through the recently added .clang-format file. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * Add a .clang-formatBen Widawsky2019-05-091-0/+13
|/ | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* Add $stop to documentationClifford Wolf2019-05-091-3/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove added newline (by re-running minisat 00_UPDATE.sh)Clifford Wolf2019-05-081-1/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #991 from kristofferkoch/gcc9-warningsClifford Wolf2019-05-085-5/+9
|\ | | | | Fix all warnings that occurred when compiling with gcc9
| * Fix all warnings that occurred when compiling with gcc9Kristoffer Ellersgaard Koch2019-05-085-5/+9
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* | Merge pull request #998 from mdaiter/get_bool_attribute_optsClifford Wolf2019-05-081-4/+8
|\ \ | | | | | | Minor optimization to get_attribute_bool
| * | Minor optimization to get_attribute_boolMatthew Daiter2019-05-071-4/+8
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* | | Add test case from #997Clifford Wolf2019-05-071-0/+12
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix handling of partial init attributes in write_verilog, fixes #997Clifford Wolf2019-05-071-1/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #996 from mdaiter/ceil_log2_optsClifford Wolf2019-05-072-3/+5
|\ \ \ | | | | | | | | Optimize ceil_log2 function
| * | | Optimize ceil_log2 functionMatthew Daiter2019-05-072-3/+5
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* | | Add "synth_xilinx -arch"Clifford Wolf2019-05-071-1/+13
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | More opt_clean cleanupsClifford Wolf2019-05-071-26/+36
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-0619-51/+810
|\ \ | | | | | | Add specify parser
| * | Improve tests/various/specify.ysClifford Wolf2019-05-061-2/+32
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add "real" keyword to ilang formatClifford Wolf2019-05-063-2/+12
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-063-12/+32
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| * | | Improve write_verilog specify supportClifford Wolf2019-05-043-16/+75
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Update READMEClifford Wolf2019-05-041-5/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | More testingEddie Hung2019-05-032-2/+5
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| * | | Fix spacingEddie Hung2019-05-031-6/+6
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