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* ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.whitequark2020-02-071-65/+84
| | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
* Merge pull request #1682 from YosysHQ/eddie/opt_after_techmapEddie Hung2020-02-058-5/+9
|\ | | | | synth_*: call 'opt -fast' after 'techmap'
| * synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-058-5/+9
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* shiftx2mux: fix select out of boundsEddie Hung2020-02-053-2/+14
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* Merge pull request #1576 from YosysHQ/eddie/opt_merge_initEddie Hung2020-02-052-1/+65
|\ | | | | opt_merge: discard \init of '$' cells with 'Q' port when merging
| * Merge remote-tracking branch 'origin/master' into eddie/opt_merge_initEddie Hung2020-01-28190-4933/+9266
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| * | Add $_FF_ and $_SR* courtesy of @mwkmwkmwkEddie Hung2019-12-202-23/+33
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| * | More stringent check for flop cellsEddie Hung2019-12-201-2/+4
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| * | opt_merge to discard \init of '$' cells with 'Q' port when mergingEddie Hung2019-12-131-0/+11
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| * | Add testcaseEddie Hung2019-12-131-0/+49
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* | | Merge pull request #1650 from YosysHQ/eddie/shiftx2muxEddie Hung2020-02-054-39/+185
|\ \ \ | | | | | | | | techmap LSB-first for compatible $shift/$shiftx cells
| * \ \ Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-0577-1944/+4467
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| * | | | Update tests with reduced areaEddie Hung2020-01-212-6/+6
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| * | | | Explicitly create separate $mux cellsEddie Hung2020-01-211-2/+2
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| * | | | Fix tests -- when Y_WIDTH is non-pow-2Eddie Hung2020-01-211-3/+4
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| * | | | Move from +/shiftx2mux.v into +/techmap.v; cleanupEddie Hung2020-01-214-77/+73
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| * | | | New techmap +/shiftx2mux.v which decomposes LSB first; better for ABCEddie Hung2020-01-213-0/+149
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* | | | | abc9_ops: -reintegrate to use derived_type for box_portsEddie Hung2020-02-052-2/+22
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* | | | Merge pull request #1638 from YosysHQ/eddie/fix1631Eddie Hung2020-02-052-6/+143
|\ \ \ \ | | | | | | | | | | clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
| * | | | More rigorous testEddie Hung2020-01-161-7/+34
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| * | | | clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*Eddie Hung2020-01-152-6/+116
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* | | | | Merge pull request #1661 from YosysHQ/eddie/abc9_requiredEddie Hung2020-02-0512-242/+809
|\ \ \ \ \ | | | | | | | | | | | | abc9: add support for required times
| * | | | | abc9_ops: -check for negative arrival/required timesEddie Hung2020-01-271-4/+22
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| * | | | | Fix typoEddie Hung2020-01-271-1/+1
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| * | | | | Merge branch 'eddie/abc9_refactor' into eddie/abc9_requiredEddie Hung2020-01-2726-246/+537
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| * \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-153-3/+16
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| * | | | | | | Update README.md for (* abc9_required *)Eddie Hung2020-01-151-4/+9
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| * | | | | | | abc9_ops: -write_box is empty, output a dummy box to prevent ABC errorEddie Hung2020-01-154-4/+4
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-151-1/+2
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| * | | | | | | | abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)Eddie Hung2020-01-142-3/+3
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| * | | | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-142-27/+19
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| * | | | | | | | | abc9_ops: -check to check abc9_{arrival,required}Eddie Hung2020-01-141-3/+30
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| * | | | | | | | | abc9_ops: implement a requireds_cacheEddie Hung2020-01-141-26/+34
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| * | | | | | | | | abc9_ops: generate flop box ids, add abc9_required to FD* cellsEddie Hung2020-01-143-78/+106
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| * | | | | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-142-10/+1
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| * | | | | | | | | | abc9_ops: fix -reintegrate handling of $__ABC9_DELAYEddie Hung2020-01-141-2/+3
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| * | | | | | | | | | abc9_ops: -prep_times -> -prep_delays; add docEddie Hung2020-01-142-11/+23
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| * | | | | | | | | | abc9_ops: cleanupEddie Hung2020-01-141-14/+5
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| * | | | | | | | | | abc9_ops: discard $__ABC9_DELAY boxesEddie Hung2020-01-141-7/+2
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| * | | | | | | | | | write_xaiger: skip if no arrival timesEddie Hung2020-01-141-0/+3
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| * | | | | | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-1422-389/+789
| |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required
| * \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-1211-156/+198
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| * | | | | | | | | | | | log_debug() for abc9_{arrival,required} timesEddie Hung2020-01-102-1/+15
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| * | | | | | | | | | | | Add abc9_required to DSP48E1.{A,B,C,D,PCIN}Eddie Hung2020-01-101-38/+117
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| * | | | | | | | | | | | abc9_ops -prep_times: generate flop boxes from abc9_required attrEddie Hung2020-01-102-78/+67
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| * | | | | | | | | | | | abc9_ops -prep_times: update commentEddie Hung2020-01-101-3/+4
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| * | | | | | | | | | | | Add abc9_ops -check, -prep_times, -write_box for required timesEddie Hung2020-01-103-75/+256
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| * | | | | | | | | | | | abc9_exe: -box to not require -lutEddie Hung2020-01-091-9/+4
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| * | | | | | | | | | | | write_xaiger: cleanupEddie Hung2020-01-091-17/+15
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| * | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-091-56/+50
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generated by cgit v1.2.3 (git 2.25.1) at 2025-04-16 17:37:28 +0000