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* xilinx_dsp to be sensitive to keep attributeEddie Hung2019-08-151-1/+14
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* SimplifyEddie Hung2019-08-151-4/+2
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* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-1526-2242/+2277
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| * Merge pull request #1297 from YosysHQ/eddie/fix_1284_againEddie Hung2019-08-151-2/+2
| |\ | | | | | | extract_fa: Un-inverting AND with an inverted input also inverts input to X{,N}OR
| | * Merge remote-tracking branch 'origin/master' into eddie/fix_1284_againEddie Hung2019-08-1525-2240/+2275
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| * | Merge pull request #1275 from YosysHQ/clifford/idsClifford Wolf2019-08-1523-2205/+2269
| |\ \ | | | | | | | | New ID() macro and now also use it
| | * \ Merge branch 'master' into clifford/idsClifford Wolf2019-08-155-126/+244
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| * | | Merge pull request #1295 from YosysHQ/eddie/fix_travisClifford Wolf2019-08-152-35/+6
| |\ \ \ | | | | | | | | | | Fix Travis CI
| | * | | Revert earliest to gcc-4.8, compile iverilog with default compilerEddie Hung2019-08-142-3/+3
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| | * | | Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!"Eddie Hung2019-08-141-5/+3
| | | | | | | | | | | | | | | | | | | | This reverts commit c82b2fa31f8965be2680c87af6cd9ac5d26ead4d.
| | * | | Remove .0 from clang-8.0Eddie Hung2019-08-141-2/+2
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| | * | | Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!Eddie Hung2019-08-141-3/+5
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| | * | | bionic -> xenial as its on whitelistEddie Hung2019-08-141-1/+1
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| | * | | Bump gcc from 4.8 to 4.9 as undefined referenceEddie Hung2019-08-141-36/+7
| |/ / / | | | | | | | | | | | | | | | | ... to `__warn_memset_zero_len'. Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0
| | * | Add YOSYS_NO_IDS_REFCNT configuration macroClifford Wolf2019-08-112-2/+25
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)Clifford Wolf2019-08-1110-1160/+1182
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | More improvements and cleanups in IdString subsystemClifford Wolf2019-08-113-43/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - better use of "inline" keyword - deprecate "sticky" IDs feature - improve handling of empty ID - add move constructor Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Use ID() macro in all of passes/opt/Clifford Wolf2019-08-1112-998/+998
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was obtained by running the following SED command in passes/opt/ and then using "meld foo.cc foo.cc.orig" to manually fix all resulting compiler errors. sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' *.cc Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Improve API of ID() macroClifford Wolf2019-08-111-2/+10
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | | * AND with an inverted input, causes X{,N}OR output to be inverted tooEddie Hung2019-08-141-2/+2
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| | | * Revert "Only sort leaves on non-ANDNOT/ORNOT cells"Eddie Hung2019-08-141-7/+6
| | | | | | | | | | | | | | | | This reverts commit 5ec5f6dec7d4cdcfd9e1a2cda999886605778400.
| | | * Only sort leaves on non-ANDNOT/ORNOT cellsEddie Hung2019-08-141-6/+7
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| * | Merge pull request #1294 from YosysHQ/revert-1288-eddie/fix_1284Eddie Hung2019-08-141-4/+8
| |\ \ | | | | | | | | Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves"
| | * | Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves"Eddie Hung2019-08-141-4/+8
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| * | Merge pull request #1288 from YosysHQ/eddie/fix_1284Eddie Hung2019-08-131-8/+4
| |\ \ | | | | | | | | Since $_ANDNOT_ is not symmetric, do not sort leaves
| | * | Since $_ANDNOT_ is not symmetric, do not sort leavesEddie Hung2019-08-121-8/+4
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* | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-08-151-1/+5
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| * | | xilinx: Rework labels for faster Verilator testingDavid Shah2019-08-131-1/+5
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | ffH -> ffFJKGEddie Hung2019-08-152-15/+15
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* | | | Fixes for reverting SigSpec helper functionsEddie Hung2019-08-142-10/+14
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* | | | Perform C -> PCIN optimisation after pattern matcherEddie Hung2019-08-132-19/+72
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* | | | Revert changes to RTLIL::SigSpec methodsEddie Hung2019-08-134-15/+36
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* | | | Only swap ports if $mul and not $__mulEddie Hung2019-08-131-1/+1
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* | | | Add assign PCOUT = P to DSP48E1Eddie Hung2019-08-131-0/+2
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* | | | Rename to XilinxDspPassEddie Hung2019-08-131-3/+3
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* | | | Add DSP_A_MAXWIDTH_PARTIAL, refactorEddie Hung2019-08-132-145/+111
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* | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-1276-551/+823
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| * | Merge pull request #1152 from 1138-4EB/feat-dockerSerge Bazanski2019-08-121-25/+49
| |\ \ | | | | | | | | Dockerfile
| | * | dockerfile: use 'python:3-slim-buster' base image1138-4EB2019-08-071-5/+8
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| | * | dockerfile: use PREFIX instead of cp1138-4EB2019-08-071-5/+8
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| | * | dockerfile: add ARG IMAGE, use three stages1138-4EB2019-08-071-13/+27
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| | * | dockerfile: reduce number of COPY layers1138-4EB2019-08-071-7/+4
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| | * | dockerfile: DEBIAN_FRONTEND should not be permanent1138-4EB2019-08-071-9/+16
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| * | | Merge pull request #1277 from YosysHQ/eddie/fix_1262Eddie Hung2019-08-112-66/+189
| |\ \ \ | | |_|/ | |/| | opt_expr -fine to now trim LSBs of $alu cells too
| | * | Merge remote-tracking branch 'origin/master' into eddie/fix_1262Eddie Hung2019-08-1191-640/+759
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| * | | Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adderEddie Hung2019-08-1020-180/+180
| |\ \ \ | | | | | | | | | | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
| | * | | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-1020-180/+180
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| * | | Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-1069-414/+405
| |\ \ \ | | | | | | | | | | Cleanup a few barnacles across codebase
| | * | | substr() -> compare()Eddie Hung2019-08-0731-127/+127
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| | * | | RTLIL::S{0,1} -> State::S{0,1} for headersEddie Hung2019-08-075-40/+40
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