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* - Makefile: include $(PWD) in PATH, since 'make test' can happen before ↵Siesh1oo2014-03-111-1/+1
| | | | 'make install'.
* - Makefile: fix typo in LDFLAGS: obviously -L, not -I is required hereSiesh1oo2014-03-111-1/+1
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* - Makefile: export PATH=${DESTDIR}/bin:$(PATH) and (DY)LD_LIBRARY_PATH, to ↵Siesh1oo2014-03-111-2/+6
| | | | | | | make sure our local copies of built executables and libraries are used. - Makefile: use find expression in target 'yosys-svgviewer' to find svgviewer binary (qmake will build into .app package on OSX). - Makefile: make 'test' target dependent on $(TARGETS) and $(EXTRA_TARGETS) to make sure that minisat is built.
* - Makefile: resolve merge conflict.Siesh1oo2014-03-111-5/+23
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* OSX compatible creation of stdcells.inc, using code from ↵Clifford Wolf2014-03-111-2/+3
| | | | | | github.com/Siesh1oo/yosys (see https://github.com/cliffordwolf/yosys/pull/28)
* Merged addition of SED makefile variable from github.com/Siesh1oo/yosysClifford Wolf2014-03-112-2/+3
| | | | (see https://github.com/cliffordwolf/yosys/pull/28)
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-1111-13/+52
| | | | (see https://github.com/cliffordwolf/yosys/pull/28)
* Added support for `line compiler directiveClifford Wolf2014-03-111-0/+11
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* Fixed memory corruption in passes/abc/blifparse.ccClifford Wolf2014-03-111-1/+1
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* Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.shClifford Wolf2014-03-111-1/+1
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* Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)Clifford Wolf2014-03-111-1/+1
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* Fixed a typo in RTLIL::Module::addReduce...Clifford Wolf2014-03-101-5/+5
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* Improved verific command (added support for some operators)Clifford Wolf2014-03-101-2/+160
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* Improvements in verific commandClifford Wolf2014-03-101-59/+39
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* Added RTLIL::Module::add... helper methodsClifford Wolf2014-03-102-0/+293
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* Added "verific" commandClifford Wolf2014-03-093-2/+501
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* Fixed dumping of timing() { .. } block in libparseClifford Wolf2014-03-091-2/+3
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* Verbose reading of liberty and constr files in ABC passClifford Wolf2014-03-091-2/+2
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* Fixed bug in freduce commandClifford Wolf2014-03-071-0/+30
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* Some minor code cleanups in freduce commandClifford Wolf2014-03-071-5/+5
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* Bugfix in ilang frontend autoidx recoveryClifford Wolf2014-03-071-2/+2
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* Use log_abort() and log_assert() in BTOR backendClifford Wolf2014-03-071-18/+17
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* Added freduce -dumpClifford Wolf2014-03-061-1/+24
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* Added freduce -stopClifford Wolf2014-03-061-3/+18
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* Fixed gcc compiler warningClifford Wolf2014-03-061-1/+2
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* Fixed undef handling in opt_reduceClifford Wolf2014-03-061-2/+2
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* Fixes for improved techmap of shifts with large B inputsClifford Wolf2014-03-061-8/+8
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* Fixed use of frozen literals in SatGenClifford Wolf2014-03-061-3/+2
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* Strictly zero-extend unsigned A-inputs of shift operations in techmapClifford Wolf2014-03-061-4/+4
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* Added techmap -max_iter optionClifford Wolf2014-03-061-0/+10
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* Improved techmap of shift with wide B inputsClifford Wolf2014-03-061-13/+37
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* Strictly zero-extend unsigned A-inputs of shift operationsClifford Wolf2014-03-062-3/+3
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* Switched to EZMINISAT_SIMPSOLVER as default SAT solverClifford Wolf2014-03-051-1/+1
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* Include id2ast pointers when dumping ASTClifford Wolf2014-03-051-0/+6
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* Fixed merging of compatible wire decls in AST frontendClifford Wolf2014-03-051-1/+4
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* Bugfix in recursive AST simplificationClifford Wolf2014-03-051-10/+22
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* fixed freduce for Minisat::SimpSolver: use frozen_literal()Clifford Wolf2014-03-031-2/+2
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* ezSAT: Added frozen_literal() APIClifford Wolf2014-03-032-0/+16
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* ezSAT: Fixed handling of eliminated Literals, added auto-freeze for expressionsClifford Wolf2014-03-032-8/+23
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* Added ezSAT::eliminated API to help the SAT solver remember eliminated variablesClifford Wolf2014-03-014-3/+17
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* ezSAT bugfix: don't call virtual methods in base class constructorClifford Wolf2014-03-012-2/+5
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* Removed ezSAT::assumed() APIClifford Wolf2014-03-013-10/+0
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* Removed ezSAT built-in brute-froce solverClifford Wolf2014-03-011-102/+6
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* Fixed vhdl2verilog temp dir nameClifford Wolf2014-03-011-1/+1
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* Fixed vhdl2verilog help messageClifford Wolf2014-03-011-3/+2
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* Fixed const folding of $bu0 cellsClifford Wolf2014-02-272-1/+2
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* Fixed bit-extending in $mux argument (use $bu0 instead of $pos)Clifford Wolf2014-02-261-5/+5
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* Added support for $bu0 to SatGenClifford Wolf2014-02-261-4/+4
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* Don't blow up constants unneccessarily in Verilog frontendClifford Wolf2014-02-241-1/+1
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* Added support for Minisat::SimpSolver + ezSAT frezze() APIClifford Wolf2014-02-235-11/+79
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