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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-24 12:41:25 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-24 12:41:25 +0100 |
| commit | 6bc94b7eb2ecc7c2836c2fc10029542ce92eae11 (patch) | |
| tree | 7c6897cdcfe8e766d3b5ef5bcfd0f16beec00240 | |
| parent | dab1612f81212d1bc1c07ee77b265167861ec883 (diff) | |
| download | yosys-6bc94b7eb2ecc7c2836c2fc10029542ce92eae11.tar.gz yosys-6bc94b7eb2ecc7c2836c2fc10029542ce92eae11.tar.bz2 yosys-6bc94b7eb2ecc7c2836c2fc10029542ce92eae11.zip | |
Don't blow up constants unneccessarily in Verilog frontend
| -rw-r--r-- | frontends/ast/genrtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index bc3783bda..dda069cb8 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -906,7 +906,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) detectSignWidth(width_hint, sign_hint); is_signed = sign_hint; - return RTLIL::SigSpec(bitsAsConst(width_hint, sign_hint)); + return RTLIL::SigSpec(bitsAsConst()); } // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node |