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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-13 22:10:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:57 -0700 |
| commit | fa31e84112c004348fae30e64ca224367b71d187 (patch) | |
| tree | 3cf1bef25954219ea5646153dbde684cc99b8246 | |
| parent | 97a0a0431489568300b40c1d376af7b5d8cb7027 (diff) | |
| download | yosys-fa31e84112c004348fae30e64ca224367b71d187.tar.gz yosys-fa31e84112c004348fae30e64ca224367b71d187.tar.bz2 yosys-fa31e84112c004348fae30e64ca224367b71d187.zip | |
Fix broken test when ignoring abc9_flop with init == 1'b1
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 2794c913a..41a11e9a7 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -213,7 +213,6 @@ void prep_hier(RTLIL::Design *design, bool dff_mode) if (init != State::S0) { log_warning("Module '%s' contains a %s cell with non-zero initial state -- this is not unsupported for ABC9 sequential synthesis. Treating as a blackbox.\n", log_id(derived_module), log_id(derived_cell->type)); derived_module->set_bool_attribute(ID::abc9_flop, false); - goto skip_cell; } break; } @@ -250,8 +249,6 @@ void prep_hier(RTLIL::Design *design, bool dff_mode) cell->type = derived_type; cell->parameters.clear(); - -skip_cell: ; } } |