diff options
| -rw-r--r-- | frontends/ast/ast.cc | 4 | ||||
| -rw-r--r-- | kernel/rtlil.cc | 2 | ||||
| -rw-r--r-- | kernel/rtlil.h | 3 |
3 files changed, 4 insertions, 5 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index ba02dd4c5..57de725d8 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -997,7 +997,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump for (auto n : global_decls) (*it)->children.push_back(n->clone()); - for (auto n : design->packages){ + for (auto n : design->verilog_packages){ for (auto o : n->children) { AstNode *cloned_node = o->clone(); cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1); @@ -1023,7 +1023,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump design->add(process_module(*it, defer)); } else if ((*it)->type == AST_PACKAGE){ - design->packages.push_back((*it)->clone()); + design->verilog_packages.push_back((*it)->clone()); } else global_decls.push_back(*it); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9e09d9f04..9da6d2816 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -304,7 +304,7 @@ RTLIL::Design::~Design() { for (auto it = modules_.begin(); it != modules_.end(); ++it) delete it->second; - for (auto n : packages) + for (auto n : verilog_packages) delete n; } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 275ba6820..274f97023 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -18,7 +18,6 @@ */ #include "kernel/yosys.h" -#include "frontends/ast/ast.h" #ifndef RTLIL_H #define RTLIL_H @@ -793,7 +792,7 @@ struct RTLIL::Design int refcount_modules_; dict<RTLIL::IdString, RTLIL::Module*> modules_; - std::vector<AST::AstNode*> packages; + std::vector<AST::AstNode*> verilog_packages; std::vector<RTLIL::Selection> selection_stack; dict<RTLIL::IdString, RTLIL::Selection> selection_vars; |