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* Merge pull request #1270 from YosysHQ/eddie/alu_lcu_docClifford Wolf2019-08-101-8/+36
|\ | | | | Add a few comments to document $alu and $lcu
| * Reformat so it shows up/looks nice when "help $alu" and "help $alu+"Eddie Hung2019-08-091-25/+34
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| * A bit more on where $lcu comes fromEddie Hung2019-08-091-0/+2
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| * Add more commentsEddie Hung2019-08-091-4/+18
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| * Add a few comments to document $alu and $lcuEddie Hung2019-08-081-9/+12
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* | Merge pull request #1272 from mmicko/travis_fixClifford Wolf2019-08-101-1/+1
|\ \ | | | | | | Propagate parameters for Travis build
| * | ABC requires it like thisMiodrag Milanovic2019-08-091-1/+1
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| * | Propagate parameters for Travis buildMiodrag Milanovic2019-08-091-1/+1
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* | | Merge pull request #1274 from YosysHQ/eddie/fix_1271Clifford Wolf2019-08-101-0/+1
|\ \ \ | | | | | | | | Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro
| * | | Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithroEddie Hung2019-08-091-0/+1
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* | | Merge pull request #1276 from YosysHQ/clifford/fix1273Clifford Wolf2019-08-101-15/+54
|\ \ \ | | | | | | | | Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib
| * | | Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g ↵Clifford Wolf2019-08-091-15/+54
| |/ / | | | | | | | | | | | | | | | all", fixes #1273 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #1267 from whitequark/proc_prune-fix-1243whitequark2019-08-091-9/+7
|\ \ \ | |/ / |/| | proc_prune: fix handling of exactly identical assigns
| * | proc_prune: fix handling of exactly identical assigns.whitequark2019-08-081-9/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, in a process like: process $proc$bug.v:8$3 assign $foo \bar switch \sel case 1'1 assign $foo 1'1 assign $foo 1'1 case assign $foo 1'0 end end both of the "assign $foo 1'1" would incorrectly be removed. Fixes #1243.
* | Merge pull request #1264 from YosysHQ/eddie/fix_1254Eddie Hung2019-08-081-0/+6
|\ \ | | | | | | opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)
| * | opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)Eddie Hung2019-08-071-0/+6
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* | Merge pull request #1266 from YosysHQ/eddie/ice40_full_adderEddie Hung2019-08-0820-180/+180
|\ \ | |/ |/| Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER
| * Remove dump callEddie Hung2019-08-071-1/+0
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| * Move tests/various/opt* into tests/opt/Eddie Hung2019-08-075-1/+1
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| * Remove ice40_unlut call, simply do equiv_opt on synth_ice40Eddie Hung2019-08-071-3/+1
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| * Add testcase from removed opt_ff.{v,ys}Eddie Hung2019-08-071-0/+32
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| * Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but runEddie Hung2019-08-072-24/+0
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| * Allow whitebox modules to be overwrittenEddie Hung2019-08-072-3/+1
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| * Update CHANGELOGEddie Hung2019-08-071-0/+2
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| * Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-076-10/+128
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| * Add testEddie Hung2019-08-071-1/+10
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| * Remove ice40_unlutEddie Hung2019-08-072-107/+0
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| * Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDEREddie Hung2019-08-073-39/+14
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* Merge pull request #1248 from YosysHQ/eddie/abc9_speedupEddie Hung2019-08-074-40/+48
|\ | | | | abc9: speedup by using using "clean" more efficiently
| * Add commentEddie Hung2019-08-071-2/+3
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| * Revert "Add TODO"Eddie Hung2019-08-071-2/+0
| | | | | | | | This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
| * Add TODOEddie Hung2019-08-071-0/+2
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| * Compute box_lookup just onceEddie Hung2019-08-071-8/+24
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| * Run "clean" on mapped_mod in its own designEddie Hung2019-08-072-24/+10
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| * Run "clean -purge" on holes_module in its own designEddie Hung2019-08-071-6/+11
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* Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixesDavid Shah2019-08-071-101/+244
|\ | | | | ecp5: Make cells_sim.v consistent with nextpnr
| * ecp5: Make cells_sim.v consistent with nextpnrDavid Shah2019-08-071-101/+244
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #1213 from YosysHQ/eddie/wreduce_addClifford Wolf2019-08-075-3/+226
|\ \ | | | | | | wreduce/opt_expr: improve width reduction for $add and $sub cells
| * | Add signed opt_expr testsEddie Hung2019-08-061-0/+50
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| * | Add signed testEddie Hung2019-08-061-0/+26
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| * | Move LSB-trimming functionality from wreduce to opt_exprEddie Hung2019-08-062-23/+26
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| * | Add SigSpec::extract_end() convenience functionEddie Hung2019-08-061-0/+1
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| * | Restore original SigSpec::extract()Eddie Hung2019-08-061-1/+1
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| * | Move LSB tests from wreduce to opt_exprEddie Hung2019-08-062-99/+101
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| * | Merge remote-tracking branch 'origin/master' into eddie/wreduce_addEddie Hung2019-08-0656-172/+763
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| * | | Try and fix againEddie Hung2019-07-191-5/+4
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| * | | Add another testEddie Hung2019-07-191-1/+24
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| * | | Do not access beyond boundsEddie Hung2019-07-191-1/+1
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| * | | Add an SigSpec::at(offset, defval) convenience methodEddie Hung2019-07-191-0/+1
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| * | | Wrap A and B in sigmapEddie Hung2019-07-191-2/+2
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