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* Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlibClifford Wolf2013-03-274-5/+18
* Imported svgviewer from qt4.8Clifford Wolf2013-03-2711-0/+994
* Create nice errors when calling RTLIL::Module::derive() of base classClifford Wolf2013-03-261-3/+3
* Collect parameters in hierarchy -generate (and do nothing with them)Clifford Wolf2013-03-261-1/+8
* Tiny bugfix in simlib.vClifford Wolf2013-03-261-1/+0
* Improvements and bugfixes for generate blocks with local signalsClifford Wolf2013-03-262-4/+2
* Fixed handling of unconditional generate blocksClifford Wolf2013-03-262-1/+19
* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-255-34/+27
* Improved verbose output of subcircuitClifford Wolf2013-03-251-1/+11
* Improved method for finding fsm_expand candidatesClifford Wolf2013-03-251-5/+7
* Added hierarchy -generate command for generating skeletton modulesClifford Wolf2013-03-252-4/+172
* Changed fsm_expand to merge multiplexers more aggressivelyClifford Wolf2013-03-241-1/+4
* Renamed hansimem.v test case to mem_arst.vClifford Wolf2013-03-241-1/+0
* Fixed handling of show -viewerClifford Wolf2013-03-241-1/+1
* Fixed handling of internal signals in show commandClifford Wolf2013-03-241-2/+2
* Improved show -colors color assignmentsClifford Wolf2013-03-241-2/+3
* Added show -strech and renamed -widthlabels to -widthClifford Wolf2013-03-241-6/+36
* Added -widthlabels options to chow commandClifford Wolf2013-03-241-31/+67
* Added -notypes option to intersynth backendClifford Wolf2013-03-241-7/+18
* Reorganized TODOsClifford Wolf2013-03-241-24/+13
* Added mem2reg option to verilog frontendClifford Wolf2013-03-245-11/+31
* Fixed stdcells.v for $adff with undef reset valueClifford Wolf2013-03-241-63/+68
* Another fix in mem2reg ast simplify logicClifford Wolf2013-03-241-1/+3
* Added -colors option to show commandClifford Wolf2013-03-241-8/+35
* Added hansimem testcase (memory with async reset)Clifford Wolf2013-03-241-0/+44
* Improved mem2reg handling in ast simplifierClifford Wolf2013-03-242-5/+35
* Fixed gcc build (intersynth backend)Clifford Wolf2013-03-231-14/+14
* Tiny fixes to verilog parserClifford Wolf2013-03-232-1/+9
* Various improvements in intersynth backendClifford Wolf2013-03-231-9/+56
* Added intersynth backendClifford Wolf2013-03-232-0/+141
* Added help -write-tex-command-reference-manual optionClifford Wolf2013-03-211-0/+38
* Added eclipse CDT project files to .gitignoreClifford Wolf2013-03-211-0/+2
* Added -S option for simple synthesis to gate logicClifford Wolf2013-03-211-2/+17
* Avoid verilog-2k in verilog backendClifford Wolf2013-03-211-0/+17
* Disabled the per-default dumping of ILANG codeClifford Wolf2013-03-211-1/+6
* Added -nomap option to memory passClifford Wolf2013-03-211-5/+19
* Merge branch 'hansiglaser-master'Clifford Wolf2013-03-193-10/+57
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| * added optimizations for single-bit $eq/$ne with constant input to opt_constClifford Wolf2013-03-191-0/+25
| * improved $mux optimization in opt_constClifford Wolf2013-03-191-2/+6
| * keep $mux and $_MUX_ optimizations separate in opt_constClifford Wolf2013-03-191-3/+3
| * added a TODOJohann Glaser2013-03-181-0/+2
| * added one more suggestion to optimize MUXes in pass "opt_const"Johann Glaser2013-03-181-0/+1
| * also optimize single-bit "$mux" cells in pass "opt_const", added suggestionsJohann Glaser2013-03-181-1/+5
| * fixed a crash when lines start with whitespaceJohann Glaser2013-03-181-2/+2
| * added description of Makefile include files for build configurationJohann Glaser2013-03-181-6/+17
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* More TODOs in READMEClifford Wolf2013-03-181-1/+7
* Merge branch 'hansi'Clifford Wolf2013-03-1813-29/+30
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| * Removed date from auto-generated passes/techmap/stdcells.incClifford Wolf2013-03-181-2/+1
| * Fixed abc eeror handlingClifford Wolf2013-03-181-2/+2
| * add header to autogenerated file on its originJohann Glaser2013-03-181-1/+3
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