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author | Clifford Wolf <clifford@clifford.at> | 2013-03-24 10:40:40 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-03-24 10:40:40 +0100 |
commit | c3c9e5a02f91eeb9d0871c94c3d883feb2619e93 (patch) | |
tree | 14c054900ef23abc6e109b206d8d73b80a15aecc | |
parent | bb3357c027eb81a9308c1d52f14298192214d285 (diff) | |
download | yosys-c3c9e5a02f91eeb9d0871c94c3d883feb2619e93.tar.gz yosys-c3c9e5a02f91eeb9d0871c94c3d883feb2619e93.tar.bz2 yosys-c3c9e5a02f91eeb9d0871c94c3d883feb2619e93.zip |
Added hansimem testcase (memory with async reset)
-rw-r--r-- | tests/simple/hansimem.v | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/tests/simple/hansimem.v b/tests/simple/hansimem.v new file mode 100644 index 000000000..b02b6c686 --- /dev/null +++ b/tests/simple/hansimem.v @@ -0,0 +1,44 @@ + +module MyMem #( + parameter AddrWidth = 4, + parameter DataWidth = 4) ( + (* gentb_constant = 1 *) + input Reset_n_i, + input Clk_i, + input [AddrWidth-1:0] Addr_i, + input [DataWidth-1:0] Data_i, + output [DataWidth-1:0] Data_o, + input WR_i); + + reg Data_o; + + localparam Size = 2**AddrWidth; + + (* mem2reg *) + reg [DataWidth-1:0] Mem[Size-1:0]; + + integer i; + + always @(negedge Reset_n_i or posedge Clk_i) + begin + //$display("Data1 = %b, Data11 = %b, Data12 = %b, Data2 = %b, Data21 = %b, Data22 = %b",Data1_i,Data11,Data12,Data2_i,Data21,Data22); + if (!Reset_n_i) + begin + Data_o <= 'bx; + for (i=0; i<Size; i=i+1) + begin + Mem[i] <= 0; + end + end + else + begin + Data_o <= Mem[Addr_i]; + if (WR_i) + begin + Mem[Addr_i] <= Data_i; + end + end + end + +endmodule + |