iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed undef handling in opt_reduce	Clifford Wolf	2014-03-06	1	-2/+2
*	Fixes for improved techmap of shifts with large B inputs	Clifford Wolf	2014-03-06	1	-8/+8
*	Fixed use of frozen literals in SatGen	Clifford Wolf	2014-03-06	1	-3/+2
*	Strictly zero-extend unsigned A-inputs of shift operations in techmap	Clifford Wolf	2014-03-06	1	-4/+4
*	Added techmap -max_iter option	Clifford Wolf	2014-03-06	1	-0/+10
*	Improved techmap of shift with wide B inputs	Clifford Wolf	2014-03-06	1	-13/+37
*	Strictly zero-extend unsigned A-inputs of shift operations	Clifford Wolf	2014-03-06	2	-3/+3
*	Switched to EZMINISAT_SIMPSOLVER as default SAT solver	Clifford Wolf	2014-03-05	1	-1/+1
*	Include id2ast pointers when dumping AST	Clifford Wolf	2014-03-05	1	-0/+6
*	Fixed merging of compatible wire decls in AST frontend	Clifford Wolf	2014-03-05	1	-1/+4
*	Bugfix in recursive AST simplification	Clifford Wolf	2014-03-05	1	-10/+22
*	fixed freduce for Minisat::SimpSolver: use frozen_literal()	Clifford Wolf	2014-03-03	1	-2/+2
*	ezSAT: Added frozen_literal() API	Clifford Wolf	2014-03-03	2	-0/+16
*	ezSAT: Fixed handling of eliminated Literals, added auto-freeze for expressions	Clifford Wolf	2014-03-03	2	-8/+23
*	Added ezSAT::eliminated API to help the SAT solver remember eliminated variables	Clifford Wolf	2014-03-01	4	-3/+17
*	ezSAT bugfix: don't call virtual methods in base class constructor	Clifford Wolf	2014-03-01	2	-2/+5
*	Removed ezSAT::assumed() API	Clifford Wolf	2014-03-01	3	-10/+0
*	Removed ezSAT built-in brute-froce solver	Clifford Wolf	2014-03-01	1	-102/+6
*	Fixed vhdl2verilog temp dir name	Clifford Wolf	2014-03-01	1	-1/+1
*	Fixed vhdl2verilog help message	Clifford Wolf	2014-03-01	1	-3/+2
*	Fixed const folding of $bu0 cells	Clifford Wolf	2014-02-27	2	-1/+2
*	Fixed bit-extending in $mux argument (use $bu0 instead of $pos)	Clifford Wolf	2014-02-26	1	-5/+5
*	Added support for $bu0 to SatGen	Clifford Wolf	2014-02-26	1	-4/+4
*	Don't blow up constants unneccessarily in Verilog frontend	Clifford Wolf	2014-02-24	1	-1/+1
*	Added support for Minisat::SimpSolver + ezSAT frezze() API	Clifford Wolf	2014-02-23	5	-11/+79
*	Fixed small memory leak in Pass::call()	Clifford Wolf	2014-02-23	1	-1/+4
*	Fixed bug in generation of undefs for $memwr MUXes	Clifford Wolf	2014-02-22	1	-4/+6
*	Fixed bug (typo) in passes/opt/opt_const.cc	Clifford Wolf	2014-02-22	1	-1/+1
*	Added $lut support to blif backend (by user eddiehung from reddit)	Clifford Wolf	2014-02-22	1	-0/+23
*	Added ezMiniSat EZMINISAT_INCREMENTAL compile-time option	Clifford Wolf	2014-02-22	2	-1/+17
*	Made MiniSat solver backend configurable in ezminisat.h	Clifford Wolf	2014-02-22	2	-3/+10
*	Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst	Clifford Wolf	2014-02-21	1	-2/+6
*	Added vhdl2verilog	Clifford Wolf	2014-02-21	2	-0/+155
*	Progress in presentation	Clifford Wolf	2014-02-21	6	-32/+113
*	Better handling of nameDef and nameRef in edif backend	Clifford Wolf	2014-02-21	1	-21/+27
*	Fixed instantiating multi-bit ports in edif backend	Clifford Wolf	2014-02-21	1	-2/+4
*	Use private namespace in mem_simple_4x1_map	Clifford Wolf	2014-02-21	1	-4/+4
*	Added tests/techmap/mem_simple_4x1	Clifford Wolf	2014-02-21	8	-0/+215
*	Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param	Clifford Wolf	2014-02-21	1	-17/+65
*	Progress in presentation	Clifford Wolf	2014-02-21	5	-19/+177
*	Progress in presentation	Clifford Wolf	2014-02-20	4	-11/+51
*	Added _TECHMAP_REPLACE_ feature to techmap	Clifford Wolf	2014-02-20	1	-4/+21
*	Added "extract -ignore_parameters" and "extract -ignore_param ..."	Clifford Wolf	2014-02-20	1	-0/+79
*	Added "extract -map %<design_name>"	Clifford Wolf	2014-02-20	1	-10/+30
*	Added "design -push" and "design -pop"	Clifford Wolf	2014-02-20	2	-8/+49
*	Progress in presentation	Clifford Wolf	2014-02-20	5	-0/+207
*	Added connwrappers command	Clifford Wolf	2014-02-20	2	-0/+206
*	Cleanups in handling of read_verilog -defer and -icells	Clifford Wolf	2014-02-20	1	-6/+7
*	Progress in presentation	Clifford Wolf	2014-02-20	10	-10/+152
*	Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)	Clifford Wolf	2014-02-19	2	-0/+170