| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add ExclusiveDatabase to check exclusive $eq/$logic_not cell results | Eddie Hung | 2019-06-07 | 1 | -1/+64 |
| | | |||||
| * | Add @cliffordwolf freduce testcase | Eddie Hung | 2019-06-07 | 2 | -0/+30 |
| | | |||||
| * | Add nonexclusive test from @cliffordwolf | Eddie Hung | 2019-06-07 | 2 | -0/+28 |
| | | |||||
| * | Resolve @cliffordwolf comment on redundant check | Eddie Hung | 2019-06-07 | 1 | -10/+2 |
| | | |||||
| * | Resolve @cliffordwolf comment on sigmap | Eddie Hung | 2019-06-07 | 1 | -2/+2 |
| | | |||||
| * | Another muxpack test | Eddie Hung | 2019-06-07 | 2 | -0/+32 |
| | | |||||
| * | Fix and test for balanced case | Eddie Hung | 2019-06-06 | 3 | -10/+55 |
| | | |||||
| * | Fix warnings | Eddie Hung | 2019-06-06 | 2 | -3/+3 |
| | | |||||
| * | Support cascading $pmux.A with $mux.A and $mux.B | Eddie Hung | 2019-06-06 | 3 | -17/+65 |
| | | |||||
| * | More cleanup | Eddie Hung | 2019-06-06 | 1 | -15/+20 |
| | | |||||
| * | Fix spacing | Eddie Hung | 2019-06-06 | 1 | -6/+5 |
| | | |||||
| * | Non chain user check using next_sig | Eddie Hung | 2019-06-06 | 1 | -7/+5 |
| | | |||||
| * | Add non exclusive test | Eddie Hung | 2019-06-06 | 2 | -0/+56 |
| | | |||||
| * | Move muxpack from passes/techmap to passes/opt | Eddie Hung | 2019-06-06 | 3 | -1/+1 |
| | | |||||
| * | Update doc | Eddie Hung | 2019-06-06 | 1 | -4/+5 |
| | | |||||
| * | Add to CHANGELOG | Eddie Hung | 2019-06-06 | 1 | -0/+1 |
| | | |||||
| * | One more and tidy up | Eddie Hung | 2019-06-06 | 2 | -6/+28 |
| | | |||||
| * | Add a few more special case tests | Eddie Hung | 2019-06-06 | 2 | -0/+51 |
| | | |||||
| * | Add tests, fix for != | Eddie Hung | 2019-06-06 | 3 | -9/+110 |
| | | |||||
| * | Missing file | Eddie Hung | 2019-06-06 | 1 | -0/+232 |
| | | |||||
| * | Initial adaptation of muxpack from shregmap | Eddie Hung | 2019-06-06 | 1 | -0/+1 |
| | | |||||
| * | Merge pull request #1060 from antmicro/parsing_attr_on_port_conn | Clifford Wolf | 2019-06-06 | 14 | -10/+279 |
| |\ | | | | | Added support for parsing attributes on port connections. | ||||
| | * | Fixed memory leak. | Maciej Kurc | 2019-06-05 | 1 | -0/+4 |
| | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| | * | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ↵ | Maciej Kurc | 2019-06-04 | 4 | -0/+46 |
| | | | | | | | | | | | | | just for parsing Verilog. Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| | * | Added tests for attributes | Maciej Kurc | 2019-06-03 | 9 | -0/+219 |
| | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| | * | Added support for parsing attributes on port connections. | Maciej Kurc | 2019-05-31 | 1 | -10/+10 |
| | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | | Merge pull request #1073 from whitequark/ecp5-diamond-iob | David Shah | 2019-06-06 | 1 | -0/+15 |
| |\ \ | | | | | | | ECP5: implement most Diamond I/O buffer primitives | ||||
| | * | | ECP5: implement all Diamond I/O buffer primitives. | whitequark | 2019-06-06 | 1 | -0/+15 |
| | | | | |||||
| * | | | Merge pull request #1071 from YosysHQ/eddie/fix_1070 | Clifford Wolf | 2019-06-06 | 1 | -2/+2 |
| |\ \ \ | | | | | | | | | Fix typo in opt_rmdff causing register to be incorrectly removed | ||||
| | * | | | Fix typo in opt_rmdff | Eddie Hung | 2019-06-05 | 1 | -2/+2 |
| | | | | | |||||
| * | | | | Merge pull request #1072 from YosysHQ/eddie/fix_1069 | Clifford Wolf | 2019-06-06 | 1 | -0/+5 |
| |\ \ \ \ | | | | | | | | | | | Error out if no top module given before 'sim' | ||||
| | * | | | | Error out if no top module given before 'sim' | Eddie Hung | 2019-06-05 | 1 | -0/+5 |
| | |/ / / | |||||
| * / / / | Missing doc for -tech xilinx in shregmap | Eddie Hung | 2019-06-05 | 1 | -0/+3 |
| |/ / / | |||||
| * | | | Merge pull request #1067 from YosysHQ/clifford/fix1065 | Eddie Hung | 2019-06-05 | 1 | -1/+1 |
| |\ \ \ | | | | | | | | | Suppress driver-driver conflict warning for unknown cell types | ||||
| | * | | | Suppress driver-driver conflict warning for unknown cell types, fixes #1065 | Clifford Wolf | 2019-06-05 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | Merge pull request #1066 from YosysHQ/clifford/fix1056 | Clifford Wolf | 2019-06-05 | 1 | -1/+0 |
| |\ \ \ \ | | | | | | | | | | | Remove yosys_banner() from python wrapper init | ||||
| | * | | | | Remove yosys_banner() from python wrapper init, fixes #1056 | Clifford Wolf | 2019-06-05 | 1 | -1/+0 |
| | |/ / / | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | Major rewrite of wire selection in setundef -init | Clifford Wolf | 2019-06-05 | 1 | -30/+89 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | Indent fix | Clifford Wolf | 2019-06-05 | 1 | -23/+25 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | Merge pull request #999 from jakobwenzel/setundefInitFix | Clifford Wolf | 2019-06-05 | 1 | -16/+23 |
| |\ \ \ \ | | | | | | | | | | | initialize more registers in setundef -init | ||||
| | * | | | | initialize more registers in setundef -init | Jakob Wenzel | 2019-05-09 | 1 | -16/+23 |
| | | | | | | |||||
| * | | | | | Fix typo in fmcombine log message, fixes #1063 | Clifford Wolf | 2019-06-05 | 1 | -2/+2 |
| | |/ / / |/| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | Merge pull request #1062 from tux3/patch-1 | Clifford Wolf | 2019-06-04 | 1 | -1/+1 |
| |\ \ \ \ | | | | | | | | | | | README.md: Missing formatting for <tag> | ||||
| | * | | | | README.md: Missing formatting for <tag> | Tux3 | 2019-06-04 | 1 | -1/+1 |
| |/ / / / | |||||
| * | | | | Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_map | Eddie Hung | 2019-06-03 | 1 | -6/+5 |
| |\ \ \ \ | | | | | | | | | | | Execute techmap and arith_map simultaneously | ||||
| | * | | | | Remove extra newline | Eddie Hung | 2019-06-03 | 1 | -1/+0 |
| | | | | | | |||||
| | * | | | | Execute techmap and arith_map simultaneously | Eddie Hung | 2019-06-03 | 1 | -6/+6 |
| |/ / / / | |||||
| * | | / | Only support Symbiotic EDA flavored Verific | Clifford Wolf | 2019-06-02 | 1 | -0/+8 |
| | |_|/ |/| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Fix "tee" handling of log_streams | Clifford Wolf | 2019-05-31 | 1 | -0/+5 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ↵ | Clifford Wolf | 2019-05-30 | 1 | -0/+3 |
| | | | | | | | | | | | | | | | | | | | fixes #1055 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |