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| * | | | | | | | | | | | | | | | | | | | | | | | Check nusers of DSP output, not whole flopEddie Hung2019-08-091-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | Improve ice40_dsp for non-fully-32-bit addersEddie Hung2019-08-091-3/+8
| * | | | | | | | | | | | | | | | | | | | | | | | Add wreduce to synth_ice40 -dsp as wellEddie Hung2019-08-091-0/+1
| * | | | | | | | | | | | | | | | | | | | | | | | Another filter -> ifEddie Hung2019-08-091-2/+2
| * | | | | | | | | | | | | | | | | | | | | | | | CleanupEddie Hung2019-08-092-18/+18
| * | | | | | | | | | | | | | | | | | | | | | | | Pack partial-product adder DSP48E1 packingEddie Hung2019-08-093-10/+81
| * | | | | | | | | | | | | | | | | | | | | | | | Fix checkEddie Hung2019-08-091-4/+6
| * | | | | | | | | | | | | | | | | | | | | | | | Revert "Fix typo"Eddie Hung2019-08-091-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | Remove muxY and ffY for nowEddie Hung2019-08-082-35/+33
| * | | | | | | | | | | | | | | | | | | | | | | | Remove signed from ports in +/xilinx/dsp_map.vEddie Hung2019-08-081-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | Rework ice40_dsp to map to SB_MAC16 earlier, and check before packingEddie Hung2019-08-086-40/+119
| * | | | | | | | | | | | | | | | | | | | | | | | Combine techmap callsEddie Hung2019-08-081-2/+1
| * | | | | | | | | | | | | | | | | | | | | | | | Only pack registers if {A,B,P}REG = 0, do not pack $dffeEddie Hung2019-08-081-3/+6
| * | | | | | | | | | | | | | | | | | | | | | | | Move xilinx_dsp to before alumaccEddie Hung2019-08-081-6/+4
| * | | | | | | | | | | | | | | | | | | | | | | | Disable $dffeEddie Hung2019-08-081-8/+8
| * | | | | | | | | | | | | | | | | | | | | | | | INMODE is 5 bitsEddie Hung2019-08-081-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | Fix copy-pasta typoEddie Hung2019-08-081-2/+2
| * | | | | | | | | | | | | | | | | | | | | | | | ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinxDavid Shah2019-08-081-11/+11
| * | | | | | | | | | | | | | | | | | | | | | | | ecp5: Bring up to date with mul2dsp changesDavid Shah2019-08-082-2/+10
| * | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspDavid Shah2019-08-0852-562/+1165
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| | * | | | | | | | | | | | | | | | | | | | | | | | Fix compile errorEddie Hung2019-08-071-2/+2
| | * | | | | | | | | | | | | | | | | | | | | | | | Run "opt_expr -fine" instead of "wreduce" due to #1213Eddie Hung2019-08-071-2/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | Do not SigSpec::extract() beyond boundsEddie Hung2019-08-072-8/+10
| | * | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-0749-552/+1134
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| | * | | | | | | | | | | | | | | | | | | | | | | | | Do not pack registers if (* keep *)Eddie Hung2019-08-071-0/+20
| * | | | | | | | | | | | | | | | | | | | | | | | | | DSP48E1 sim model: add SIMD testsDavid Shah2019-08-083-3/+113
| * | | | | | | | | | | | | | | | | | | | | | | | | | DSP48E1 model: test CE inputsDavid Shah2019-08-082-7/+17
| * | | | | | | | | | | | | | | | | | | | | | | | | | DSP48E1 sim model: fix seq tests and add preadder testsDavid Shah2019-08-082-6/+91
| * | | | | | | | | | | | | | | | | | | | | | | | | | DSP48E1 sim model: seq test workingDavid Shah2019-08-083-16/+60
| * | | | | | | | | | | | | | | | | | | | | | | | | | DSP48E1 sim model: Comb, no pre-adder, mode workingDavid Shah2019-08-082-8/+13
| * | | | | | | | | | | | | | | | | | | | | | | | | | [wip] sim model testingDavid Shah2019-08-084-15/+77
| * | | | | | | | | | | | | | | | | | | | | | | | | | [wip] sim model testingDavid Shah2019-08-083-40/+360
| * | | | | | | | | | | | | | | | | | | | | | | | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-071-6/+82
| * | | | | | | | | | | | | | | | | | | | | | | | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-23/+120
| * | | | | | | | | | | | | | | | | | | | | | | | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-8/+75
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| * | | | | | | | | | | | | | | | | | | | | | | | | Add comment about supporting $dffe in ice40_dspEddie Hung2019-08-011-0/+1
| * | | | | | | | | | | | | | | | | | | | | | | | | Pack P register properlyEddie Hung2019-08-011-2/+4
| * | | | | | | | | | | | | | | | | | | | | | | | | Trim Y_WIDTHEddie Hung2019-08-011-5/+3
| * | | | | | | | | | | | | | | | | | | | | | | | | Add DSP_SIGNEDONLY backEddie Hung2019-08-011-0/+16
| * | | | | | | | | | | | | | | | | | | | | | | | | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTHEddie Hung2019-08-012-5/+12
| * | | | | | | | | | | | | | | | | | | | | | | | | Change $__softmul back to $mulEddie Hung2019-08-011-0/+1
| * | | | | | | | | | | | | | | | | | | | | | | | | Cope with sign extension in mul2dspEddie Hung2019-08-012-14/+14
| * | | | | | | | | | | | | | | | | | | | | | | | | Revert "Do not do sign extension in techmap; let packer do it"Eddie Hung2019-08-011-5/+14
| * | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-0125-86/+219
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| * | | | | | | | | | | | | | | | | | | | | | | | | | Fix B_WIDTH > DSP_B_MAXWIDTH caseEddie Hung2019-08-011-32/+14
| * | | | | | | | | | | | | | | | | | | | | | | | | | CO is sign extension only if signed multiplierEddie Hung2019-08-011-1/+6
| * | | | | | | | | | | | | | | | | | | | | | | | | | Fix typoEddie Hung2019-08-011-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | | | Do not compute sign bit if result is zeroEddie Hung2019-07-311-1/+2
| * | | | | | | | | | | | | | | | | | | | | | | | | | For signed multipliers, compute sign bit separately...Eddie Hung2019-07-311-23/+42
| * | | | | | | | | | | | | | | | | | | | | | | | | | Restore old CO behaviourEddie Hung2019-07-311-6/+7
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