iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Rip out some more stuff	Eddie Hung	2019-02-13	1	-36/+0
*	Rip out unused functions in abc9	Eddie Hung	2019-02-12	1	-416/+61
*	Add support for read_aiger -wideports	Eddie Hung	2019-02-12	2	-6/+15
*	Add support for read_aiger -map	Eddie Hung	2019-02-12	2	-4/+82
*	Parse 'm' in xaiger	Eddie Hung	2019-02-12	1	-20/+57
*	WIP for ABC with aiger	Eddie Hung	2019-02-12	1	-130/+19
*	Add read_xaiger	Eddie Hung	2019-02-11	2	-27/+108
*	Add write_xaiger	Eddie Hung	2019-02-11	2	-21/+11
*	Copy backends/aiger/aiger.cc to xaiger.cc	Eddie Hung	2019-02-08	1	-0/+788
*	Compile abc9	Eddie Hung	2019-02-08	2	-8/+9
*	Refactor kernel/cost.h definition into cost.cc	Eddie Hung	2019-02-08	3	-49/+78
*	Copy abc.cc to abc9.cc	Eddie Hung	2019-02-08	1	-0/+1868
*	addDff -> addDffGate as per @daveshah1	Eddie Hung	2019-02-08	1	-1/+1
*	Fix tabulation	Eddie Hung	2019-02-08	1	-28/+28
*	-module_name arg to go before -clk_name	Eddie Hung	2019-02-08	1	-7/+7
*	Support and differentiate between ASCII and binary AIG testing	Eddie Hung	2019-02-08	2	-2/+6
*	Add missing "[options]" to read_blif help	Eddie Hung	2019-02-08	1	-1/+1
*	Allow module name to be determined by argument too	Eddie Hung	2019-02-08	2	-14/+44
*	Refactor into AigerReader class	Eddie Hung	2019-02-08	2	-79/+92
*	Parse binary AIG files	Eddie Hung	2019-02-08	1	-49/+164
*	Add binary AIGs converted from AAG	Eddie Hung	2019-02-08	14	-0/+51
*	Refactor to parse_aiger_header()	Eddie Hung	2019-02-08	1	-26/+32
*	Add comment	Eddie Hung	2019-02-08	1	-0/+1
*	Handle reset logic in latches	Eddie Hung	2019-02-08	1	-2/+17
*	Change literal vars from int to unsigned	Eddie Hung	2019-02-08	1	-1/+1
*	Create clk outside of latch loop	Eddie Hung	2019-02-08	1	-7/+9
*	Handle latch symbols too	Eddie Hung	2019-02-08	1	-3/+1
*	Remove return after log_error	Eddie Hung	2019-02-08	1	-27/+9
*	Add support for symbol tables	Eddie Hung	2019-02-08	1	-1/+49
*	Stub for binary AIGER	Eddie Hung	2019-02-08	1	-3/+8
*	Refactor	Eddie Hung	2019-02-06	1	-1/+8
*	Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig	Eddie Hung	2019-02-06	7	-50/+172
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\| *	Refactor	Eddie Hung	2019-02-06	1	-21/+5
\| *	write_verilog to cope with init attr on q when -noexpr	Eddie Hung	2019-02-06	1	-2/+32
\| *	Add INIT parameter to all ff/latch cells	Eddie Hung	2019-02-06	2	-43/+86
\| *	Add tests for simple cases using defparam	Eddie Hung	2019-02-06	1	-0/+21
\| *	Add -B option to autotest.sh to append to backend_opts	Eddie Hung	2019-02-06	1	-2/+4
\| *	Extend testcase	Eddie Hung	2019-02-06	1	-2/+34
\| *	Add testcase	Eddie Hung	2019-02-06	1	-0/+10
\| *	Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::...	Clifford Wolf	2019-02-06	1	-1/+1
* \|	Revert most of autotest.sh; for non *.v use Yosys to translate	Eddie Hung	2019-02-06	1	-7/+9
* \|	Rename ASCII tests	Eddie Hung	2019-02-06	15	-0/+0
* \|	WIP	Eddie Hung	2019-02-06	3	-0/+247
* \|	Add tests	Eddie Hung	2019-02-04	16	-8/+109
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*	Merge pull request #798 from mmicko/master	Clifford Wolf	2019-01-27	1	-1/+1
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\| *	Fixed Anlogic simulation model	Miodrag Milanovic	2019-01-25	1	-1/+1
* \|	Merge pull request #800 from whitequark/write_verilog_tribuf	Clifford Wolf	2019-01-27	1	-0/+12
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\| * \|	write_verilog: write $tribuf cell as ternary.	whitequark	2019-01-27	1	-0/+12
* \| \|	Merge branch 'whitequark-write_verilog_keyword'	Clifford Wolf	2019-01-27	5	-69/+27
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\| * \|	Remove asicworld tests for (unsupported) switch-level modelling	Clifford Wolf	2019-01-27	4	-69/+0