| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-27 | 0 | -0/+0 |
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| | * | synth_xilinx -arch -> -family, consistent with older synth_intel | Eddie Hung | 2019-06-27 | 1 | -7/+8 |
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| | * | Merge pull request #1142 from YosysHQ/clifford/fix1132 | Eddie Hung | 2019-06-27 | 2 | -6/+345 |
| | |\ | | | | | | | Fix handling of partial covers in muxcover | ||||
| | | * | Copy tests from eddie/fix1132 | Eddie Hung | 2019-06-27 | 1 | -0/+320 |
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| | | * | Fix handling of partial covers in muxcover, fixes #1132 | Clifford Wolf | 2019-06-27 | 1 | -6/+25 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymux | Eddie Hung | 2019-06-27 | 2 | -12/+34 |
| | |\ \ | | |/ | |/| | synth_xilinx: Add -nocarry and -nowidelut options | ||||
| | * | | Merge pull request #1137 from mmicko/cell_sim_fix | Clifford Wolf | 2019-06-26 | 2 | -14/+1 |
| | |\ \ | | | | | | | | | Simulation model verilog fix | ||||
| | | * | | Simulation model verilog fix | Miodrag Milanovic | 2019-06-26 | 2 | -14/+1 |
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| | * | | Improve opt_clean handling of unused public wires | Clifford Wolf | 2019-06-26 | 1 | -2/+2 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Improve BTOR2 handling of undriven wires | Clifford Wolf | 2019-06-26 | 1 | -3/+27 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131 | Clifford Wolf | 2019-06-26 | 1 | -1/+1 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Do not clean up buffer cells with "keep" attribute, closes #1128 | Clifford Wolf | 2019-06-26 | 1 | -1/+1 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Escape scope names starting with dollar sign in smtio.py | Clifford Wolf | 2019-06-26 | 1 | -1/+4 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Add more ECP5 Diamond flip-flops. | whitequark | 2019-06-26 | 2 | -30/+91 |
| | | | | | | | | | | | | | | | | This includes all I/O registers, and a few more regular FFs where it was convenient. | ||||
| * | | | Add warning if synth_xilinx -abc9 with family != xc7 | Eddie Hung | 2019-06-27 | 1 | -0/+2 |
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| * | | | Remove unneeded include | Eddie Hung | 2019-06-27 | 1 | -3/+0 |
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| * | | | Merge origin/master | Eddie Hung | 2019-06-27 | 10 | -65/+480 |
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| * | | | Fix spacing | Eddie Hung | 2019-06-26 | 1 | -38/+38 |
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| * | | | Improve debugging message for comb loops | Eddie Hung | 2019-06-26 | 1 | -4/+6 |
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| * | | | Add WE to ECP5 dist RAM's abc_scc_break too | Eddie Hung | 2019-06-26 | 1 | -1/+1 |
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| * | | | Update comment on boxes | Eddie Hung | 2019-06-26 | 2 | -4/+6 |
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| * | | | Add "WE" to dist RAM's abc_scc_break | Eddie Hung | 2019-06-26 | 1 | -3/+3 |
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| * | | | Support more than one port in the abc_scc_break attr | Eddie Hung | 2019-06-26 | 1 | -38/+42 |
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| * | | | Add write_xaiger into CHANGELOG | Eddie Hung | 2019-06-26 | 1 | -0/+1 |
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| * | | | Merge branch 'koriakin/xc7nocarrymux' into xaig | Eddie Hung | 2019-06-26 | 0 | -0/+0 |
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| | * | | Grrr | Eddie Hung | 2019-06-26 | 1 | -2/+2 |
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| * | | | Remove unused var | Eddie Hung | 2019-06-26 | 1 | -1/+1 |
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| * | | | Add _nowide variants of LUT libraries in -nowidelut flows | Eddie Hung | 2019-06-26 | 4 | -13/+44 |
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| * | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-06-26 | 1 | -2/+10 |
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| | * \ \ | Merge pull request #1136 from YosysHQ/xaig_ice40_wire_del | Eddie Hung | 2019-06-26 | 1 | -2/+10 |
| | |\ \ \ | | | | | | | | | | | abc9: Add wire delays to synth_ice40 | ||||
| | | * | | | abc9: Add wire delays to synth_ice40 | David Shah | 2019-06-26 | 1 | -2/+10 |
| | |/ / / | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | | Merge branch 'koriakin/xc7nocarrymux' into xaig | Eddie Hung | 2019-06-26 | 0 | -0/+0 |
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| | * | | | Fix spacing | Eddie Hung | 2019-06-26 | 1 | -5/+5 |
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| * | | | | Merge branch 'koriakin/xc7nocarrymux' into xaig | Eddie Hung | 2019-06-26 | 0 | -0/+0 |
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| | * | | | Oops. Actually use nocarry flag as spotted by @koriakin | Eddie Hung | 2019-06-26 | 1 | -5/+7 |
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| * | | | | Merge branch 'koriakin/xc7nocarrymux' into xaig | Eddie Hung | 2019-06-26 | 2 | -9/+26 |
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| | * | | synth_ecp5 rename -nomux to -nowidelut, but preserve former | Eddie Hung | 2019-06-26 | 1 | -6/+6 |
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| | * | | Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into ↵ | Eddie Hung | 2019-06-26 | 1 | -4/+24 |
| | |\ \ | | |/ | |/| | | | | koriakin/xc7nocarrymux | ||||
| | | * | synth_xilinx: Add -nocarry and -nomux options. | Marcin Kościelnicki | 2019-04-30 | 1 | -7/+26 |
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| * | | | Missing muxpack.o in Makefile | Eddie Hung | 2019-06-25 | 1 | -0/+1 |
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| * | | | Realistic delays for RAM32X1D too | Eddie Hung | 2019-06-25 | 1 | -2/+2 |
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| * | | | Add RAM32X1D box info | Eddie Hung | 2019-06-25 | 2 | -4/+12 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-25 | 13 | -14/+1029 |
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| | * | | Add testcase from #335, fixed by #1130 | Eddie Hung | 2019-06-25 | 1 | -0/+28 |
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| | * | | Merge pull request #1130 from YosysHQ/eddie/fix710 | Clifford Wolf | 2019-06-25 | 3 | -6/+33 |
| | |\ \ | | | | | | | | | memory_dff: walk through more than one mux for computing read enable | ||||
| | | * | | Fix spacing | Eddie Hung | 2019-06-25 | 1 | -4/+3 |
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| | | * | | Move only one consumer check outside of while loop | Eddie Hung | 2019-06-25 | 1 | -6/+5 |
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| | | * | | Walk through as many muxes as exist for rd_en | Eddie Hung | 2019-06-24 | 1 | -8/+16 |
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| | | * | | Add test | Eddie Hung | 2019-06-24 | 2 | -1/+22 |
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| | * | | | Merge pull request #1129 from YosysHQ/eddie/ram32x1d | Eddie Hung | 2019-06-25 | 5 | -20/+73 |
| | |\ \ \ | | | | | | | | | | | Add RAM32X1D support | ||||
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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