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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 19:58:09 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 19:58:09 -0700 |
| commit | b7bef15b16abf1674d9c2efc58536db3abaf0e3d (patch) | |
| tree | 236edc2cc49e7ded7640f54ddb5f0def3ccd4730 | |
| parent | 26efd6f0a9ee5930efef7e1d00724bbb87489885 (diff) | |
| download | yosys-b7bef15b16abf1674d9c2efc58536db3abaf0e3d.tar.gz yosys-b7bef15b16abf1674d9c2efc58536db3abaf0e3d.tar.bz2 yosys-b7bef15b16abf1674d9c2efc58536db3abaf0e3d.zip | |
Add "WE" to dist RAM's abc_scc_break
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 04381e3b9..4ecf8277b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -281,7 +281,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -(* abc_box_id = 4, abc_scc_break="D" *) +(* abc_box_id = 4, abc_scc_break="D,WE" *) module RAM32X1D ( output DPO, SPO, input D, WCLK, WE, @@ -299,7 +299,7 @@ module RAM32X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* abc_box_id = 5, abc_scc_break="D" *) +(* abc_box_id = 5, abc_scc_break="D,WE" *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -317,7 +317,7 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* abc_box_id = 6, abc_scc_break="D" *) +(* abc_box_id = 6, abc_scc_break="D,WE" *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, |