iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added Xilinx example for Basys3 board	Clifford Wolf	2015-02-01	9	-1/+84
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*	Added EDIF backend support for multi-bit cell ports	Clifford Wolf	2015-02-01	1	-11/+10
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*	Added missing ports and parameters to xilinx brams	Clifford Wolf	2015-02-01	1	-4/+18
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*	Added "make mklibyosys", some minor API changes	Clifford Wolf	2015-02-01	7	-11/+70
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*	Minor README changes	Clifford Wolf	2015-02-01	1	-3/+2
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*	Removed TODO list from README file	Clifford Wolf	2015-02-01	1	-30/+0
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*	Added yosys_banner(), Updated Copyright range	Clifford Wolf	2015-02-01	4	-26/+31
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*	Added <algorithm> include to hashlib.h	Clifford Wolf	2015-02-01	1	-0/+1
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*	Using selections in "ls" command	Clifford Wolf	2015-02-01	1	-34/+30
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*	Shorter "dump" options	Clifford Wolf	2015-01-31	1	-4/+4
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*	Bugfix in opt_const $eq -> buffer code	Clifford Wolf	2015-01-31	1	-4/+4
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*	Log msg change	Clifford Wolf	2015-01-31	1	-1/+1
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*	Fixed equiv_make for partially undriven nets (e.g. after "clean -purge")	Clifford Wolf	2015-01-31	1	-12/+31
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*	Added "equiv_induct -undef"	Clifford Wolf	2015-01-31	2	-6/+51
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*	Added "equiv_simple -undef"	Clifford Wolf	2015-01-31	2	-17/+61
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*	Added "equiv_make -blacklist <file> -encfile <file>"	Clifford Wolf	2015-01-31	4	-5/+189
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*	Synced RTLIL::unescape_id() to log_id() behavior	Clifford Wolf	2015-01-30	1	-3/+9
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*	Added "fsm -encfile"	Clifford Wolf	2015-01-30	3	-14/+50
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*	More log_id() stuff	Clifford Wolf	2015-01-30	1	-3/+7
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*	Some cleanups in log.cc	Clifford Wolf	2015-01-30	1	-14/+16
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*	Improved an error message	Clifford Wolf	2015-01-28	1	-1/+1
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*	Fixed bug in equiv_miter	Clifford Wolf	2015-01-28	1	-6/+6
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*	Added "sat -show-ports"	Clifford Wolf	2015-01-27	1	-2/+7
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*	Bugfix in resource sharing test	Clifford Wolf	2015-01-27	1	-1/+1
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*	Updaed ABC to hg rev 61ad5f908c03	Clifford Wolf	2015-01-27	1	-1/+1
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*	Rethrow with "catch(...) throw;"	Clifford Wolf	2015-01-25	3	-6/+6
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*	Added equiv_remove	Clifford Wolf	2015-01-25	2	-0/+84
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*	Added equiv_miter	Clifford Wolf	2015-01-25	2	-0/+344
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*	Added ENABLE_NDEBUG makefile options	Clifford Wolf	2015-01-24	12	-12/+33
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*	Added #ifdef NDEBUG for log_assert()	Clifford Wolf	2015-01-24	1	-1/+5
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*	Fixed xilinx FDSE sim model	Clifford Wolf	2015-01-24	1	-2/+2
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*	Various equiv_* improvements	Clifford Wolf	2015-01-24	4	-14/+20
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*	Added dict/pool.sort()	Clifford Wolf	2015-01-24	7	-50/+80
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*	Improvements in equiv_make, equiv_induct	Clifford Wolf	2015-01-22	2	-0/+46
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*	Improved xdot calling	Clifford Wolf	2015-01-22	1	-2/+2
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*	Added equiv_induct	Clifford Wolf	2015-01-22	2	-0/+182
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*	Various equiv_simple improvements	Clifford Wolf	2015-01-22	2	-25/+69
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*	Moved equiv stuff to passes/equiv/	Clifford Wolf	2015-01-22	5	-3/+5
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*	Progress in equiv_simple	Clifford Wolf	2015-01-21	2	-41/+110
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*	Fixed opt_muxtree performance bug	Clifford Wolf	2015-01-21	1	-11/+28
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*	Faster "make clean-abc"	Clifford Wolf	2015-01-20	1	-2/+2
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*	README stuff	Clifford Wolf	2015-01-20	1	-2/+3
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*	Added equiv_simple	Clifford Wolf	2015-01-19	2	-0/+188
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*	Added equiv_status	Clifford Wolf	2015-01-19	2	-0/+95
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*	Added equiv_make command	Clifford Wolf	2015-01-19	4	-1/+260
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*	Added $equiv cell type	Clifford Wolf	2015-01-19	4	-2/+33
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2015-01-18	1	-0/+6
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\| *	Merge pull request #47 from mschmoelzer/master	Clifford Wolf	2015-01-18	1	-0/+6
\| \|\ \| \| \| \| \| \|	Add "echo-yosys-ver" and "echo-git-rev" Makefile targets.
\| \| *	Add "echo-yosys-ver" and "echo-git-rev" Makefile targets.	Martin Schmölzer	2015-01-18	1	-0/+6
\| \|/ \| \| \| \| \| \| \| \| \| \| \| \|	These Makefile targets simply echo the corresponding Makefile variable, simplifying package build scripts. Signed-off-by: Martin Schmölzer <mschmoelzer@gmail.com>
* \|	Various cleanups in xilinx techlib	Clifford Wolf	2015-01-18	7	-9/+110
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