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* Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-110-0/+0
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| * write_xaiger: create holes_sigmap before modificationsEddie Hung2020-01-111-1/+2
* | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-1110-116/+170
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| * Merge pull request #1625 from YosysHQ/eddie/abc9_mfsEddie Hung2020-01-116-86/+115
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| | * write_xaiger: sort holes by offset as well as port_idEddie Hung2020-01-111-1/+2
| | * abc9: remove -nomfs optionEddie Hung2020-01-111-12/+2
| | * Merge remote-tracking branch 'origin/master' into eddie/abc9_mfsEddie Hung2020-01-116-32/+48
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| * | Merge pull request #1622 from YosysHQ/clifford/onpassregEddie Hung2020-01-113-1/+20
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| | * | Add Pass::on_register() and Pass::on_shutdown()Clifford Wolf2020-01-093-1/+20
| * | | Merge pull request #1624 from YosysHQ/eddie/abc9_leakEddie Hung2020-01-101-4/+2
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| | * | | abc9: fix memory leakEddie Hung2020-01-101-4/+2
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| * / / Bump versionClifford Wolf2020-01-091-1/+1
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| | * Bump ABCREV for upstream fixEddie Hung2020-01-111-1/+1
| | * write_xaiger: cleanup holes generationEddie Hung2020-01-081-80/+89
| | * write_xaiger: holes PIs only if whiteboxEddie Hung2020-01-081-13/+18
| | * Fix abc9_xc7.box commentsEddie Hung2020-01-071-7/+14
| | * Merge remote-tracking branch 'origin/master' into eddie/abc9_mfsEddie Hung2020-01-0730-1078/+1575
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| | * | Add testcase from #1459Eddie Hung2020-01-061-0/+25
| | * | Re-enable &mfs for synth_{ecp5,xilinx}Eddie Hung2020-01-062-3/+2
| | * | Bump ABCREVEddie Hung2020-01-061-1/+1
* | | | Merge branch 'eddie/abc9_refactor' of github.com:YosysHQ/yosys into eddie/abc...Eddie Hung2020-01-114-109/+92
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| * | | | abc9: cleanupEddie Hung2020-01-113-45/+38
| * | | | abc9_ops: fix reintegration by removing optimised-away boxesEddie Hung2020-01-091-56/+50
| * | | | read_aiger: more accurate debug messageEddie Hung2020-01-091-2/+4
| * | | | read_aiger: do not double-count outputs for flopsEddie Hung2020-01-091-6/+0
* | | | | CleanupEddie Hung2020-01-081-5/+3
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* | | | Fix abc9 help, add labelsEddie Hung2020-01-081-58/+71
* | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-071-7/+14
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| * | | Fix abc9_xc7.box commentsEddie Hung2020-01-071-7/+14
| * | | scc to use design->selected_modules() which avoids black/white-boxesEddie Hung2020-01-071-26/+25
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* | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-074-6/+38
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| * | Bump ABCREV for upstream fixEddie Hung2020-01-071-1/+1
| * | Merge pull request #1618 from YosysHQ/eddie/aiger_fixesEddie Hung2020-01-074-8/+42
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| | * | read_aiger: consistency between ascii and binary; also name latchesEddie Hung2020-01-071-3/+9
| | * | Add testcasesEddie Hung2020-01-072-0/+17
| | * | tests/aiger: write Yosys outputEddie Hung2020-01-071-2/+2
| | * | read_aiger: connect identical signals togetherEddie Hung2020-01-071-0/+1
| | * | read_aiger: cope with latches and POs with same nameEddie Hung2020-01-071-2/+12
| | * | read_aiger: default -clk_name to be emptyEddie Hung2020-01-071-1/+1
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* | | read_aiger fixesEddie Hung2020-01-071-5/+5
* | | tests/aiger: write Yosys outputEddie Hung2020-01-071-2/+2
* | | abc9_ops -reintegrate: process box connectionsEddie Hung2020-01-071-27/+134
* | | read_aiger: do not process box connections, work standaloneEddie Hung2020-01-071-115/+46
* | | Fix tabs and cleanupEddie Hung2020-01-071-38/+38
* | | read_aiger: consistency between ascii and binaryEddie Hung2020-01-071-13/+7
* | | abc_exe: move 'count_outputs' check to abcEddie Hung2020-01-072-54/+50
* | | Merge branch 'master' into eddie/abc9_refactorEddie Hung2020-01-061-3/+3
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| * | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2020-01-0626-1066/+1529
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| | * \ Merge pull request #1181 from YosysHQ/xaig_dffEddie Hung2020-01-0626-1066/+1529
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| * / | Fix DSP48E1 simEddie Hung2020-01-061-3/+3
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