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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-07 11:43:28 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-07 11:43:28 -0800 |
| commit | b94cf0c1266f6f3daea809323f0bba0dc5d69e1a (patch) | |
| tree | 0629be7d3e790ebfe197c0bf363db74b9e599a13 | |
| parent | baba33fbd391d31187695a8d0d9937249a472b2e (diff) | |
| download | yosys-b94cf0c1266f6f3daea809323f0bba0dc5d69e1a.tar.gz yosys-b94cf0c1266f6f3daea809323f0bba0dc5d69e1a.tar.bz2 yosys-b94cf0c1266f6f3daea809323f0bba0dc5d69e1a.zip | |
read_aiger: connect identical signals together
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 04530e562..f7b9146ce 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -280,6 +280,7 @@ end_of_header: if (wire) { // Could have been renamed by a latch module->swap_names(wire, outputs[l1]); + module->connect(outputs[l1], wire); goto next; } wire = outputs[l1]; |